Datasheet

REV. C–12–
AD8011
40
30
20
010152025
C
L
(pF)
10
R
SERIES
(⍀)
5
Figure 12. Recommended R
SERIES
vs. Capacitive
Load for
≤ 30 ns Settling to 0.1%
OPTIMIZING FLATNESS
As mentioned, the previous ac transfer equations are based on a
simplified single-pole model. Due to the device’s internal para-
sitics (primarily C
P
1/C
P
1B and C
P
2 in Figure 6) and external
package/board parasites (partially represented in Figure 12) the
computed BW, using the previous V
O
(s) equation, typically will
be lower than the AD8011’ s measured small signal BW. See
data sheet Bode plots.
With only internal parasitics included, the BW is extended due
to the complex pole pairs created primarily by C
P
1/C
P
2B and
C
P
2 versus the single-pole assumption shown above. This
results in a design controlled, closed-loop damping factor (␨) of
nominally 0.6 resulting in the CLBW increasing by approxi-
mately 1.3⫻ higher than the computed single-pole value above
for optimized external gains of +2/–1. As external noninverting
gain (G) is increased, the actual closed-loop bandwidth versus
the computed single-pole ac response is in closer agreement.
Inverting pin and external component capacitance (designated C
P
)
will further extend the CLBW due to the closed-loop zero created
by C
P
and R
N
储R
F
when operating in the noninverting mode. Using
proper R
F
component and layout techniques (see the Layout
Considerations section), this capacitance should be about 1.5 pF.
This results in a further incremental BW increase of almost 2⫻
(versus the computed value) for G = +1 decreasing and approach-
ing its complex pole pair BW for gains approaching +6 or higher.
As previously discussed, the single-pole response begins to corre-
late well. Note that a pole is also created by 1/2 g
mf
and C
P
, which
prevents the AD8011 from becoming unstable. This parasitic
has the greatest effect on BW and peaking for low positive gains
as the data sheet Bode plots clearly show. For inverting operation,
C
P
has relatively much less effect on CLBW variation.
11
10
9
8
7
5
4
3
6
2
1
1 10 100 500
FREQUENCY
(
MHz
)
GAIN (dB)
R
F
= 1k⍀
R
F
= 750⍀
V
S
= ⴞ5V
G = +2
V
IN
= 200mV
Figure 13. Flatness vs. Feedback
Output pin and external component capacitance (designated C
L
)
will further extend the devices BW and can also cause peaking
below and above the CLBW if too high. In the time domain,
poor step settling characteristics (ringing up to about 2 GHz
and excessive overshoot) can result. For high C
L
values greater
than about 5 pF, an external series damping resistor is recom-
mended. For light loads, any output capacitance will reflect on
A2’s output (Z2 of buffer A3) as both added capacitance near
the CLBW (CLBW > f
T
/B) and eventually negative resistance at
much higher frequencies. These added effects are proportional
to the load C. This reflected capacitance and negative resistance
has the effect of both reducing A2’s phase margin and causing
high frequency, L ⫻ C, peaking respectively. Using an external
series resistor (as previously specified) reduces these unwanted
effects by creating a reflected zero to A2’s output, which will
reduce the peaking and eliminate ringing. For heavy resistive
loads, relatively more load C would be required to cause these
same effects.
High inductive parasitics, especially on the supplies and inverting/
noninverting inputs, can cause modulated low level R
F
ringing on
the output in the transient domain. Proper R
F
component and
board layout practices need to be observed. Relatively high para-
sitic lead inductance (roughly L >15 nh) can result in L ⫻ C
underdamped ringing. Here L/C means all associated input pins,
external components, and lead frame strays, including collector
to substrate device capacitance. In the ac domain, this L ⫻ C
resonance effect would typically not appear in the pass band of
the amplifier but would appear in the open-loop response at
frequencies well above the CLBW of the amplifier.