Datasheet

REV. C
AD8011
–11–
1E+03 1E+04 1E+05 1E+06 1E+07 1E+08 1E+09
FREQUENCY (Hz)
140
120
100
80
60
20
0
40
GAIN (dB ⍀)
0
PHASE (Degrees)
–40
–80
–120
–160
–200
–240
–280
PHASE
GAIN
T
O
(s)
Figure 9. Open-Loop Transimpedance Gain
Note that the ac open-loop plots in Figures 8, 9, and 10 are based
on the full SPICE AD8011 simulations and do not include
external parasitics (see equations below). Nevertheless, these ac
loop equations still provide a good approximation to simulated
and actual performance up to the CLBW of the amplifier. Typi-
cally, g
mc
⫻ R1 is –4, resulting in A
O
(s) having a right half plane
pole. In the time domain (inverse Laplace of A
O
), it appears as
unstable, causing V
O
to exponentially rail out of its linear region.
When the loop is closed however, the BW is greatly extended and
the transimpedance gain, T
O
(s), overrides and directly controls
the amplifiers stability behavior due to Z
I
approaching 1/2 g
mf
for s>>1/τ1 (see Figure 10). This can be seen by the Z
I
(s) and
A
V
(s) noninverting transfer equations below.
Zs
g
mc
R
S
g
mc
R
g
mf
S
I
()
( – )
–
()
=
×
×
+








×+
11
1
11
1
211
τ
τ
As
G
G
A
R
T
S
G
g
mf
T
R
T
V
O
F
OO
F
O
()=
++






+








+








11
2
1
τ
1E+03 1E+04 1E+05 1E+06 1E+07 1E+08 1E+09
400
370
340
310
280
220
190
FREQUENCY (Hz)
250
RESISTANCE (⍀)
20
PHASE (Degrees)
0
–20
–40
–120
160
130
100
–140
–160
–180
–60
–80
–100
SERIES 1
IMPEDANCE
Z
I
(s)
SERIES 2
PHASE
Figure 10. Open-Loop Inverting Input Impedance
Z
I
(s) goes positive real and approaches 1/2 g
mf
as ␻ approaches
(g
mc
冤 R1 – 1)/τ1. This results in the input resistance for the A
V
(s)
complex term being 1/2 g
mf
, the parallel thermal emitter
resistances of Q3/Q4. Using the computed CLBW from A
V
(s)
and the nominal design values for the other parameters, results in
a closed-loop 3 dB BW equal to the open-loop corner frequency
(1/2 πτ1) × 1/[G/(2 g
mf
⫻ T
O
) + R
F
/T
O
]. For a fixed R
F
, the
3 dB BW is controlled by the R
F
/T
O
term for low gains and
G/(2 g
mf
⫻ T
O
) for high gains. For example, using nominal design
parameters and R
1
= 1 kΩ (which results in a nominal T
O
of
1.2 MΩ), the computed BW is 80 MHz for G = 0 (inverting
I-V mode with R
N
removed) and 40 MHz for G = +10/–9.
DRIVING CAPACITIVE LOADS
The AD8011 was designed primarily to drive nonreactive loads.
If driving loads with a capacitive component is desired, the best
settling response is obtained by the addition of a small series
resistance as shown in Figure 11. The accompanying graph shows
the optimum value for R
SERIES
versus capacitive load. It is worth
noting that the frequency response of the circuit when driving
large capacitive loads will be dominated by the passive roll-off
of R
SERIES
and C
L
.
1k⍀
R
L
1k⍀
C
L
R
SERIES
1k⍀
AD8011
Figure 11. Driving Capacitive Load