Datasheet

AD80066
Rev. A | Page 7 of 20
ANALOG
INPUTS
CDSCLK1
PIXEL n
PIXEL (n + 1) PIXEL (n + 2)
CDSCLK2
ADCCLK
OUTPUT
DATA
(D[7:0])
NOTES
1. IN 1-CHANNEL CDS MODE. THE CDSCLK1 FALLING EDGE AND THE CDSCLK2 RISING EDGE MUST OCCUR WHILE ADCCLK IS LOW.
LOW
BYTE
HIGH
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
08552-006
t
AD
t
C1
t
AD
t
C2ADR
t
OD
t
C1C2
PIXEL (n – 4)
t
C2ADF
t
ADCCLK
t
ADCCLK
t
C2
PIXEL (n – 4) PIXEL (n – 3) PIXEL (n – 3) PIXEL (n – 2) PIXEL (n – 2)
t
C2C1
t
PRB
Figure 6. 1-Channel CDS Mode Timing
PIXEL n (A, B, C, D)
t
AD
t
C2
t
C2ADF
t
ADC2
t
C2ADR
t
ADCCLK
t
ADCCLK
t
OD
B(n – 2) C(n – 2) C(n – 2) D(n – 2) D(n – 2) D(n) D(n) A(n) A(n)
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
t
PRA
PIXEL (n + 1)
ANALOG
INPUTS
CDSCLK2
ADCCLK
OUTPUT
DATA
(D[7:0])
A(n – 1) A(n – 1) B(n – 1) B(n – 1) C(n – 1) C(n – 1)
08552-007
Figure 7. 4-Channel SHA Mode Timing