Datasheet

AD80066
Rev. A | Page 6 of 20
t
OD
t
ADCCLK
t
ADCCLK
ANALOG
INPUTS
CDSCLK1
CDSCLK2
ADCCLK
OUTPUT
DATA
(D[7:0])
PIXEL n (A, B, C) PIXEL (n + 1) PIXEL (n + 2)
t
AD
t
AD
t
PRA
t
C2C1
t
C1
t
C2
t
C1C2
t
C2ADF
t
C2ADR
t
ADC2
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
B(n – 2)A(n – 2) B(n – 2) C(n – 2) C(n – 2) A(n – 1) A(n – 1) B(n – 1) B(n – 1) C(n – 1) C(n – 1) A(n) A(n) B(n) B(n)
08552-004
Figure 4. 3-Channel CDS Mode Timing
CH 1 (n – 2) CH 2 (n – 2) CH 1 (n – 1) CH 2 (n – 1) CH 1 (n)
ANALOG
INPUTS
CDSCLK1
CDSCLK2
ADCCLK
OUTPUT
DATA
(D[7:0])
PIXEL n
PIXEL (n + 1) PIXEL (n + 2)
t
AD
t
AD
t
PRA
t
C2C1
t
C1
t
ADCCLK
t
ADCCLK
t
C2
t
C1C2
t
C2ADR
t
C2ADF
t
ADC2
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
08552-005
Figure 5. 2-Channel CDS Mode Timing