Datasheet

AD80066
Rev. A | Page 5 of 20
TIMING SPECIFICATIONS
T
MIN
to T
MAX
, AVDD = 5 V, DRVDD = 5 V.
Table 3.
Parameter Symbol Min Typ Max Unit
CLOCK PARAMETERS
4-Channel Pixel Rate t
PRA
166 ns
1-Channel Pixel Rate t
PRB
83 ns
ADCCLK Pulse Width t
ADCCLK
20 ns
CDSCLK1 Pulse Width t
C1
15 ns
CDSCLK2 Pulse Width t
C2
15 ns
CDSCLK1 Falling
1
to CDSCLK2 Rising t
C1C2
0 ns
ADCCLK Falling to CDSCLK2 Rising t
ADC2
0 ns
CDSCLK2 Rising to ADCCLK Rising t
C2ADR
5 ns
CDSCLK2 Falling
1
to ADCCLK Falling t
C2ADF
20 ns
CDSCLK2 Falling
1
to CDSCLK1 Rising t
C2C1
5 ns
Aperture Delay for CDS Clocks t
AD
2 ns
SERIAL INTERFACE
Maximum SCLK Frequency, Write Operation f
SCLK
50 MHz
Maximum SCLK Frequency, Read Operation f
SCLK
25 MHz
SLOAD to SCLK Setup Time t
LS
5 ns
SCLK to SLOAD Hold Time t
LH
5 ns
SDATA to SCLK Rising Setup Time t
DS
2 ns
SCLK Rising to SDATA Hold Time t
DH
2 ns
SCLK Falling to SDATA Valid t
RDV
10 ns
DATA OUTPUT
Output Delay t
OD
8 ns
Latency (Pipeline Delay) 3 (fixed) Cycles
1
CDSCLKx falling edges should not occur within the first 10 ns following an ADCCLK edge.
Timing Diagrams
ANALOG
INPUTS
CDSCLK1
CDSCLK2
ADCCLK
OUTPUT
DATA
(D[7:0])
PIXEL n (A,B,C,D) PIXEL (n + 1)
t
AD
t
AD
t
C2ADF
t
C2ADR
t
ADC2
t
OD
t
ADCCLK
t
ADCCLK
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
HIGH
BYTE
LOW
BYTE
C(n – 2)B(n – 2) C(n – 2) D(n – 2) D(n – 2) A(n – 1) A(n – 1) B(n – 1) B(n – 1) C(n – 1) C(n – 1) D(n – 1) D(n – 1) A(n) A(n) B(n)
t
PRA
t
C2C1
t
C1C2
t
C2
t
C1
0
8552-003
Figure 3. 4-Channel CDS Mode Timing