Datasheet

AD80066
Rev. A | Page 14 of 20
INTERNAL REGISTER MAP
Table 7. Internal Register Map
Address Data Bits
Register Name A3 A2 A1 A0 D8 D7 D6 D5 D4 D3 D2 D1 D0
Configuration 0 0 0 0 0 0 0 VREF 2/1 byte CDS on Input range Fast/slow Power on
Mux 0 0 0 1 0 0 0 0 Ch. order Ch. A Ch. B Ch. C Ch. D
Gain A 0 0 1 0 0 0 0 MSB LSB
Gain B 0 0 1 1 0 0 0 MSB LSB
Gain C 0 1 0 0 0 0 0 MSB LSB
Gain D 0 1 0 1 0 0 0 MSB LSB
Offset A 0 1 1 0 MSB LSB
Offset B 0 1 1 1 MSB LSB
Offset C 1 0 0 0 MSB LSB
Offset D 1 0 0 1 MSB LSB