Datasheet

AD7991/AD7995/AD7999
Rev. B | Page 6 of 28
A Version
2
Y Version
Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments
LOGIC INPUTS (SDA, SCL)
Input High Voltage, V
INH
0.7 (V
DD
) 0.7 (V
DD
) V V
DD
= 2.7 V to 5.5 V
0.9 (V
DD
) V V
DD
= 2.35 V to 2.7 V
Input Low Voltage, V
INL
0.3 (V
DD
) 0.3 (V
DD
) V V
DD
= 2.7 V to 5.5 V
0.1 (V
DD
) V V
DD
= 2.35 V to 2.7 V
Input Leakage Current, I
IN
±1 ±1 μA V
IN
= 0 V or V
DD
Input Capacitance, C
IN
7
10 10 pF
Input Hysteresis, V
HYST
0.1 (V
DD
) 0.1 (V
DD
) V
LOGIC OUTPUTS (OPEN
DRAIN)
Output Low Voltage, V
OL
0.4 0.4 V I
SINK
= 3 mA
0.6 0.6 V I
SINK
= 6 mA
Floating-State Leakage
Current
±1 ±1 μA
Floating-State Output
Capacitance
7
10 10 pF
Output Coding Straight (natural) binary Straight (natural) binary
THROUGHPUT RATE 18 × (1/f
SCL
) 18 × (1/f
SCL
)
f
SCL
≤ 1.7 MHz; see the Serial Interface
section
17.5 × (1/f
SCL
) +
2 μs
17.5 × (1/f
SCL
) +
2 μs
f
SCL
> 1.7 MHz; see the Serial Interface
section
POWER REQUIREMENTS
3
V
REF
= V
DD
; for f
SCL
= 3.4 MHz,
clock stretching is implemented
V
DD
2.7 5.5 2.7 5.5 V
I
DD
Digital inputs = 0 V or V
DD
0.09/0.25 mA V
DD
= 3.3 V/5.5 V, 400 kHz f
SCL
ADC Operating,
Interface Active
(Fully Operational)
0.25 0.25/0.8 mA V
DD
= 3.3 V/5.5 V, 3.4 MHz f
SCL
0.07/0.16 mA V
DD
= 3.3 V/5.5 V, 400 kHz f
SCL
Power-Down, Interface
Active
8
0.26 0.26/0.85 mA V
DD
= 3.3 V/5.5 V, 3.4 MHz f
SCL
Power-Down, Interface
Inactive
8
1 1/1.6 μA V
DD
= 3.3 V/5.5 V
Power Dissipation
0.3/1.38 mW V
DD
= 3.3 V/5.5 V, 400 kHz f
SCL
ADC Operating,
Interface Active
(Fully Operational)
0.83 0.83/4.4 mW V
DD
= 3.3 V/5.5 V, 3.4 MHz f
SCL
0.24/0.88 mW V
DD
= 3.3 V/5.5 V, 400 kHz f
SCL
Power-Down, Interface
Active
8
0.86 0.86/4.68 mW V
DD
= 3.3 V/5.5 V, 3.4 MHz f
SCL
Power-Down, Interface
Inactive
8
3.3 3.3/8.8 μW V
DD
= 3.3 V/5.5 V
1
Functional from V
DD
= 2.35 V.
2
A Version tested at V
DD
= 3.3 V and f
SCL
= 3.4 MHz. Functionality tested at f
SCL
= 400 kHz.
3
Sample delay and bit trial delay enabled, t
1
= t
2
= 0.5/f
SCL
.
4
For f
SCL
up to 400 kHz, clock stretching is not implemented. Above f
SCL
= 400 kHz, clock stretching is implemented.
5
See the Terminology section.
6
For f
SCL
≤ 1.7 MHz, clock stretching is not implemented; for f
SCL
> 1.7 MHz, clock stretching is implemented.
7
Guaranteed by initial characterization.
8
See the Reading from the AD7991/AD7995/AD7999 section.