Datasheet

AD7991/AD7995/AD7999
Rev. B | Page 25 of 28
PLACING THE AD7991/AD7995/AD7999 INTO HIGH SPEED MODE
High speed mode communication commences after the master
addresses all devices connected to the bus with the master code,
00001XXX, to indicate that a high speed mode transfer is to
begin. No device connected to the bus is allowed to acknowledge
the high speed master code; therefore, the code is followed by a
NO ACK (see Figure 26). The master must then issue a repeated
start, followed by the device address and an R/
W
bit. The selected
device then acknowledges its address.
All devices continue to operate in high speed mode until the
master issues a stop condition. When the stop condition is
issued, the devices return to fast mode.
To guarantee performance above f
SCL
= 1.7 MHz, the user must
perform clock stretching—that is, the clock must be held high—for
2 µs after the ninth clock rising edge (see Figure 27). Therefore,
the clock must be held high for 2 µs after the device starts to power
up (see the Reading from the AD7991/AD7995/AD7999 section).
0
6461-028
SDA
ACK BY
ADC
START BY
MASTER
HS MODE MASTER CODE SERIAL BUS ADDRESS BYTE
NO ACK
191 9
01 0 0A0XX1000
SCL
0
0
1
X
Sr
FAST MODE
HIGH SPEED MODE
Figure 26. Placing the Part into High Speed Mode
06461-030
S
DA
119 9
D10 D9 D8A01000 000
SCL
1 D11
1
D7 D6 D5 D2 D1 D0D4 D3
SCL (CONTINUED)
SDA (CONTINUED)
CH
ID1
CH
ID0
R/W
9
START BY
MASTER
ACK BY
ADC
NO ACK BY
MASTER
ACK BY
MASTER
STOP BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
MOST SIGNIFICANT DATA BYTE FROM ADC
FRAME 3
LEAST SIGNIFICANT DATA BYTE FROM ADC
CLOCK HIGH TIME = 2µs
Figure 27. Reading Two Bytes of Data from the Conversion Result Register in High Speed Mode for AD7991