Datasheet

AD7991/AD7995/AD7999
Rev. B | Page 21 of 28
SAMPLE DELAY AND BIT TRIAL DELAY
It is recommended that no I
2
C bus activity occur while a
conversion is taking place (see Figure 27 and the Placing the
AD7991/AD7995/AD7999 into High Speed Mode section).
However, if this is not always possible, then in order to maintain
the performance of the ADC, Bits D0 and D1 in the configuration
register are used to delay critical sample intervals and bit trials
from occurring while there is activity on the I
2
C bus. This results in
a quiet period for each bit decision. However, the sample delay
protection may introduce excessive jitter, degrading the SNR for
large signals above 300 Hz. For guaranteed ac performance, use
of clock stretching is recommended.
When Bit D0 and Bit D1 are both 0, the bit trial and sample interval
delay mechanism is implemented. The default setting of D0 and D1
is 0. To turn off both delay mechanisms, set D0 and D1 to 1.
CONVERSION RESULT REGISTER
The conversion result register is a 16-bit read-only register that
stores the conversion result from the ADC in straight binary
format. A 2-byte read is necessary to read data from this
register. Table 12 shows the contents of the first byte to be read
from AD7991/AD7995/AD7999, and Table 13 shows the
contents of the second byte to be read.
Each AD7991/AD7995/AD7999 conversion result consists of
two leading 0s, two channel identifier bits, and the 12-/10-/8-bit
data result. For the AD7995, the two LSBs (D1 and D0) of the
second read contain two trailing 0s. For the AD7999, the four
LSBs (D3, D2, D1, and D0) of the second read contain four
trailing 0s.
Table 12. Conversion Value Register (First Read)
D15 D14 D13 D12 D11 D10 D9 D8
Leading 0 Leading 0 CH
ID1
CH
ID0
MSB B10 B9 B8
Table 13. Conversion Value Register (Second Read)
D7 D6 D5 D4 D3 D2 D1 D0
B7 B6 B5 B4 B3/0 B2/0 B1/0 B0/0