Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External SOT 23 8

4-Channel, 12-/10-/8-Bit ADC with

C-Compatible Interface in 8-Lead SOT-23

AD7991/AD7995/AD7999

Rev. B

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FEATURES

12-/10-/8-bit ADCs with fast conversion time: 1 μs typical

4 analog input channels/3 analog input channels with

reference input

Specified for V

of 2.7 V to 5.5 V

Sequencer operation

Temperature range: −40°C to +125°C

C-compatible serial interface supports standard, fast,

and high speed modes

2 versions allow 2 I

C addresses

Low power consumption

Shutdown mode: 1 μA maximum

8-lead SOT-23 package

APPLICATIONS

System monitoring

Battery-powered systems

Data acquisition

Medical instruments

FUNCTIONAL BLOCK DIAGRAM

I/P

MUX

SCL

SDA

GND

AD7991/AD7995/AD7999

12-/10-/8-BIT

SAR

ADC

CONTROL

LOGIC AND

INTERFACE

IN0

06461-001

IN1

IN2

IN3

REF

T/H

Figure 1.

GENERAL DESCRIPTION

The AD7991/AD7995/AD7999 are 12-/10-/8-bit, low power,

successive approximation ADCs with an I

C®-compatible interface.

Each part operates from a single 2.7 V to 5.5 V power supply and

features a 1 µs conversion time. The track-and-hold amplifier

allows each part to handle input frequencies of up to 14 MHz,

and a multiplexer allows taking samples from four channels.

Each AD7991/AD7995/AD7999 provides a 2-wire serial

interface compatible with I

C interfaces. The AD7991 and

AD7995 come in two versions and each version has an

individual I

C address. This allows two of the same devices to be

connected to the same I

C bus. Both versions support standard,

fast, and high speed I

C interface modes. The AD7999 comes in

one version.

The AD7991/AD7995/AD7999 normally remain in a shutdown

state, powering up only for conversions. The conversion process

is controlled by a command mode, during which each I

C read

operation initiates a conversion and returns the result over the

C bus.

When four channels are used as analog inputs, the reference for

the part is taken from V

; this allows the widest dynamic input

range to the ADC. Therefore, the analog input range to the

ADC is 0 V to V

. An external reference, applied through the

IN3

REF

input, can also be used with this part.

PRODUCT HIGHLIGHTS

1. Four single-ended analog input channels, or three single-

ended analog input channels and one reference input channel.

2. I

C-compatible serial interface. Standard, fast, and high

speed modes.

3. Automatic shutdown.

4. Reference derived from the power supply or external

reference.

5. 8-lead SOT-23 package.

Table 1. Related Devices

Device Resolution Input Channels

AD7998 12 8

AD7997 10 8

AD7994 12 4

AD7993 10 4

AD7992 12 2

Summary of content (28 pages)

PAGE 1
4-Channel, 12-/10-/8-Bit ADC with I2C-Compatible Interface in 8-Lead SOT-23 AD7991/AD7995/AD7999 FEATURES FUNCTIONAL BLOCK DIAGRAM VDD 12-/10-/8-bit ADCs with fast conversion time: 1 μs typical 4 analog input channels/3 analog input channels with reference input Specified for VDD of 2.7 V to 5.
PAGE 2
AD7991/AD7995/AD7999 TABLE OF CONTENTS Features .............................................................................................. 1 Converter Operation.................................................................. 17 Applications....................................................................................... 1 Typical Connection Diagram ................................................... 18 Functional Block Diagram ..............................................................
PAGE 3
AD7991/AD7995/AD7999 SPECIFICATIONS AD7991 1 The temperature range of the Y version is −40°C to +125°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V, VREF = 2.5 V, fSCL = 3.4 MHz, and TA = TMIN to TMAX. Table 2. Parameter DYNAMIC PERFORMANCE 2, 3 Signal-to-Noise and Distortion (SINAD) 4 Signal-to-Noise Ratio (SNR)4 Total Harmonic Distortion (THD)4 Peak Harmonic or Spurious Noise (SFDR)4 Intermodulation Distortion (IMD)4 Min Y Version Typ Max 69.5 70 70 71 −75.5 −77.5 −92 −88 −90 14 1.5 ±1 ±0.
PAGE 4
AD7991/AD7995/AD7999 Parameter LOGIC INPUTS (SDA, SCL) Input High Voltage, VINH Y Version Typ Max Min 0.7 (VDD) 0.9 (VDD) Input Low Voltage, VINL Input Leakage Current, IIN Input Capacitance, CIN 6 Input Hysteresis, VHYST LOGIC OUTPUTS (OPEN DRAIN) Output Low Voltage, VOL 0.3 (VDD) 0.1 (VDD) ±1 10 0.1 (VDD) 0.4 0.
PAGE 5
AD7991/AD7995/AD7999 AD7995 1 The temperature range for the Y version is −40°C to +125°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V, VREF = 2.5 V, fSCL = 3.4 MHz, and TA = TMIN to TMAX. Table 3. Parameter DYNAMIC PERFORMANCE 3 , 4 Min A Version 2 Typ Max Min Y Version Typ Max Unit Test Conditions/Comments See the Sample Delay and Bit Trial Delay section, fIN = 10 kHz sine wave for fSCL from 1.7 MHz to 3.
PAGE 6
AD7991/AD7995/AD7999 Parameter LOGIC INPUTS (SDA, SCL) Input High Voltage, VINH Min 0.7 (VDD) Input Low Voltage, VINL Input Leakage Current, IIN Input Capacitance, CIN 7 Input Hysteresis, VHYST LOGIC OUTPUTS (OPEN DRAIN) Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance7 Output Coding THROUGHPUT RATE A Version 2 Typ Max Min Y Version Typ Max 0.7 (VDD) 0.9 (VDD) 0.3 (VDD) 0.3 (VDD) 0.1 (VDD) ±1 10 ±1 10 0.1 (VDD) 0.
PAGE 7
AD7991/AD7995/AD7999 AD7999 1 The temperature range for the Y version is −40°C to +125°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V, VREF = 2.5 V, fSCL = 3.4 MHz, and TA = TMIN to TMAX. Table 4. Parameter DYNAMIC PERFORMANCE 3 , 4 Min Signal-to-Noise and Distortion (SINAD) 5 Total Harmonic Distortion (THD)5 Peak Harmonic or Spurious Noise (SFDR)5 Intermodulation Distortion (IMD)5 49.
PAGE 8
AD7991/AD7995/AD7999 Parameter LOGIC INPUTS (SDA, SCL) Input High Voltage, VINH Min 0.7 (VDD) Input Low Voltage, VINL Input Leakage Current, IIN Input Capacitance, CIN 7 Input Hysteresis, VHYST LOGIC OUTPUTS (OPEN DRAIN) Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance7 Output Coding THROUGHPUT RATE A Version 2 Typ Max Y Version Typ Max Min 0.7 (VDD) 0.9 (VDD) 0.3 (VDD) 0.3 (VDD) 0.1 (VDD) ±1 10 ±1 10 0.1 (VDD) 0.
PAGE 9
AD7991/AD7995/AD7999 I2C TIMING SPECIFICATIONS Guaranteed by initial characterization. All values were measured with the input filtering enabled. CB refers to the capacitive load on the bus line, with tr and tf measured between 0.3 VDD and 0.7 VDD (see Figure 2). Unless otherwise noted, VDD = 2.7 V to 5.5 V and TA = TMIN to TMAX. Table 5.
PAGE 10
AD7991/AD7995/AD7999 Parameter t10 t11 t11A Conditions Standard mode Fast mode High speed mode CB = 100 pF maximum CB = 400 pF maximum Standard mode Fast mode High speed mode CB = 100 pF maximum CB = 400 pF maximum Standard mode Fast mode High speed mode CB = 100 pF maximum CB = 400 pF maximum Standard mode Fast mode High speed mode CB = 100 pF maximum CB = 400 pF maximum Fast mode High speed mode t12 tSP1 Limit at tMIN, tMAX Typ Max 300 20 + 0.
PAGE 11
AD7991/AD7995/AD7999 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 6.
PAGE 12
AD7991/AD7995/AD7999 SCL 1 SDA 2 VIN0 3 VIN1 4 AD7991/ AD7995/ AD7999 TOP VIEW (Not to Scale) 8 VDD 7 GND 6 VIN3/VREF 5 VIN2 06461-003 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. SOT-23 Pin Configuration Table 7. Pin Function Descriptions Pin No. 1 2 3 4 5 6 Mnemonic SCL SDA VIN0 VIN1 VIN2 VIN3/VREF 7 GND 8 VDD Description Digital Input. Serial bus clock. External pull-up resistor required. Digital I/O. Serial bus bidirectional data. Open-drain output.
PAGE 13
AD7991/AD7995/AD7999 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.0 VDD = 2.7V VREF = 2.35V fSCL = 1.7MHz 0.8 0.6 INL ERROR (LSB) 0.4 0.2 0 –0.2 –0.4 –0.2 –0.8 0 500 1000 1500 2000 2500 3000 3500 4000 –1.0 1.2 3.2 3.7 4.2 4.7 0.8 0.6 0.2 0 –0.2 –0.4 0.2 0 –0.4 –0.6 –0.8 –0.8 1500 2000 2500 3000 3500 4000 CODE –1.0 1.2 ENOB VDD = 3V 10.0 66 9.5 INL ERROR (LSB) 68 SINAD VDD = 3V 64 9.0 0.2 0 –0.2 –0.4 –0.6 62 5 6 REFERENCE VOLTAGE (V) 60 VDD = 5V VREF = 2.
PAGE 14
AD7991/AD7995/AD7999 1.0 –70 fSCL = 1.7MHz 0.8 0.4 –80 0 –0.2 –0.6 0 500 1000 1500 2000 2500 3000 3500 4000 CODE –100 100 10 INPUT FREQUENCY (kHz) Figure 13. THD vs. Input Frequency, VREF = 2.5 V, fSCL = 1.7 MHz Without Clock Stretching Figure 10. DNL Error, VDD = 5 V, VREF = 2.5 V, fSCL = 1.7 MHz Without Clock Stretching 800 96 +125°C +85°C +25°C –40°C 600 400 2 3 4 5 6 VDD (V) VDD = 3V 94 93 92 VDD = 5V 91 90 89 06461-035 200 95 VREF = VDD fSCL = 1.
PAGE 15
AD7991/AD7995/AD7999 3 0 16384 POINT FFT fS = 95kSPS fSCL = 1.71MHz fIN = 10.13kHz SNR = 71.77dB SINAD = 71.45dB THD = –82.43dB SFDR = –95.02dB 2 –60 –80 VDD = 5V 1 –120 0 5 10 15 20 25 30 35 40 FREQUENCY (kHz) 45 Figure 16. Dynamic Performance, fSCL = 1.71 MHz Without Clock Stretching, VDD = 5 V, Full-Scale Input, Seven-Term Blackman-Harris Window 0 0 500 1000 1500 SCL FREQUENCY (kHz) Figure 17. Power vs. SCL Frequency, VREF = 2.5 V Rev.
PAGE 16
AD7991/AD7995/AD7999 TERMINOLOGY Signal-to-Noise and Distortion (SINAD) Ratio The measured ratio of signal-to-noise and distortion at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of the nonfundamental signals excluding dc, up to half the sampling frequency (fS/2). The ratio is dependent on the number of quantization levels in the digitization process: the more levels, the smaller the quantization noise.
PAGE 17
AD7991/AD7995/AD7999 THEORY OF OPERATION The AD7991/AD7995/AD7999 provide the user with a 4-channel multiplexer, an on-chip track-and-hold, an ADC, and an I2Ccompatible serial interface, all housed in an 8-lead SOT-23 package that offers the user considerable space-saving advantages over alternative solutions. The AD7991/AD7995/AD7999 normally remains in a powerdown state while not converting. Therefore, when supplies are first applied, the part is in a power-down state.
PAGE 18
AD7991/AD7995/AD7999 TYPICAL CONNECTION DIAGRAM ANALOG INPUT Figure 22 shows the typical connection diagram for the AD7991/AD7995/AD7999. Figure 21 shows an equivalent circuit of the AD7991/AD7995/ AD7999 analog input structure. The two diodes, D1 and D2, provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal does not exceed the supply rails by more than 300 mV.
PAGE 19
AD7991/AD7995/AD7999 VDD = 5V VREF = VDD TEMPERATURE = TA fSCL = 1.7MHz –20 –30 –40 –50 5.1kΩ –60 2kΩ –70 1.3kΩ –80 240Ω –90 56Ω –100 1 10 ANALOG INPUT FREQUENCY (kHz) 100 06461-025 When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance depends on the amount of THD that can be tolerated. THD increases as the source impedance increases and performance degrades. Figure 23 shows the THD vs.
PAGE 20
AD7991/AD7995/AD7999 INTERNAL REGISTER STRUCTURE CONFIGURATION REGISTER The configuration register is an 8-bit write-only register that is used to set the operating modes of the AD7991/AD7995/AD7999. The bit functions are outlined in Table 10. A single-byte write is necessary when writing to the configuration register. D7 is the MSB. When the master writes to the AD7991/AD7995/AD7999, the first byte is written to the configuration register. Table 9.
PAGE 21
AD7991/AD7995/AD7999 SAMPLE DELAY AND BIT TRIAL DELAY CONVERSION RESULT REGISTER 2 It is recommended that no I C bus activity occur while a conversion is taking place (see Figure 27 and the Placing the AD7991/AD7995/AD7999 into High Speed Mode section). However, if this is not always possible, then in order to maintain the performance of the ADC, Bits D0 and D1 in the configuration register are used to delay critical sample intervals and bit trials from occurring while there is activity on the I2C bus.
PAGE 22
AD7991/AD7995/AD7999 SERIAL INTERFACE Control of the AD7991/AD7995/AD7999 is accomplished via the I2C-compatible serial bus. The AD7991/AD7995/AD7999 is connected to this bus as a slave device under the control of a master device, such as the processor. 4. Data is sent over the serial bus in sequences of nine clock pulses—eight bits of data followed by an acknowledge bit from the receiver of data.
PAGE 23
AD7991/AD7995/AD7999 WRITING TO THE AD7991/AD7995/AD7999 By default, each part operates in read-only mode and all four channels are selected as enabled in the configuration register. To write to the AD7991/AD7995/AD7999 configuration register, the user must first address the device. 1 The configuration register is an 8-bit register; therefore, only one byte of data can be written to this register.
PAGE 24
AD7991/AD7995/AD7999 READING FROM THE AD7991/AD7995/AD7999 Reading data from the conversion result register is a 2-byte operation, as shown in Figure 25. Therefore, a read operation always involves two bytes. read operation and should not affect the read operation. The master reads back two bytes of data. On the ninth SCLK rising edge of the second byte, if the master sends an ACK, it keeps reading conversion results and the AD7991/AD7995/AD7999 powers up and performs a second conversion.
PAGE 25
AD7991/AD7995/AD7999 PLACING THE AD7991/AD7995/AD7999 INTO HIGH SPEED MODE High speed mode communication commences after the master addresses all devices connected to the bus with the master code, 00001XXX, to indicate that a high speed mode transfer is to begin. No device connected to the bus is allowed to acknowledge the high speed master code; therefore, the code is followed by a NO ACK (see Figure 26). The master must then issue a repeated start, followed by the device address and an R/W bit.
PAGE 26
AD7991/AD7995/AD7999 MODE OF OPERATION The AD7991/AD7995/AD7999 powers up in shutdown mode. After the master addresses the AD7991/AD7995/AD7999 with the correct I2C address, the ADC acknowledges the address. In response, the AD7991/AD7995/AD7999 power up. During this wake up time, the AD7991/AD7995/AD7999 exit shutdown mode and begin to acquire the analog input (acquisition phase). By default, all channels are selected.
PAGE 27
AD7991/AD7995/AD7999 OUTLINE DIMENSIONS 3.00 2.90 2.80 1.70 1.60 1.50 8 7 6 5 1 2 3 4 PIN 1 INDICATOR 3.00 2.80 2.60 0.65 BSC 1.95 BSC 1.45 MAX 0.95 MIN 0.15 MAX 0.05 MIN 0.38 MAX 0.22 MIN 0.22 MAX 0.08 MIN SEATING PLANE 8° 4° 0° 0.60 BSC COMPLIANT TO JEDEC STANDARDS MO-178-BA 0.60 0.45 0.30 121608-A 1.30 1.15 0.90 Figure 29.