Datasheet

AD7988-1/AD7988-5 Data Sheet
Rev. D | Page 6 of 24
500µA I
OL
500µA I
OH
1.4V
TO SDO
C
L
20pF
10231-002
Figure 2. Load Circuit for Digital Interface Timing
X% VIO
1
Y% VIO
1
V
IH
2
V
IL
2
V
IL
2
V
IH
2
t
DELAY
t
DELAY
1
FOR VIO ≤ 3.0V, X = 90 AND Y = 10; FOR VIO > 3.0V X = 70, AND Y = 30.
2
MINIMUM V
IH
AND MAXIMUM V
IL
USED. SEE DIGITAL INPUTS
SPECIFICATIONS IN TABLE 3.
10231-003
Figure 3. Voltage Levels for Timing