Datasheet

Data Sheet AD7988-1/AD7988-5
Rev. D | Page 19 of 24
CS MODE 4-WIRE
This mode is typically used when multiple AD7988-x devices
are connected to an SPI-compatible digital host.
A connection diagram example using two AD7988-x devices is
shown in Figure 36, and the corresponding timing is given in
Figure 37.
With SDI high, a rising edge on CNV initiates a conversion,
selects the
CS
mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
time elapses and then held high for the maximum conversion time.
When the conversion is complete, the AD7988-x enters the
acquisition phase and powers down. Each ADC result can
be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are then
clocked by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can be used to capture
the data, a digital host using the SCK falling edge allows a faster
reading rate, provided that it has an acceptable hold time. After
the 16th SCK falling edge or when SDI goes high, whichever is
earlier, SDO returns to high impedance and another AD7988-x
can be read.
DIGITAL HOST
CONVERT
CLK
DATA IN
AD7988-1/
AD7988-5
SDO
CNV
SCK
AD7988-1/
AD7988-5
SDO
CNV
SCK
CS1
CS2
SDI SDI
10231-037
Figure 36. 4-Wire
CS
Mode Connection Diagram
t
CONV
t
CYC
ACQUISITION
ACQUISITION
t
ACQ
t
SCK
t
SCKH
t
SCKL
CONVERSION
SCK
CNV
t
SSDICNV
t
HSDICNV
SDO
D15 D13D14 D1 D0 D15 D14 D1
D0
t
HSDO
t
EN
1 2 3 14 15 16 17 18 30 31 32
t
DSDO
t
DIS
SDI (CS1)
SDI (CS2)
10231-038
Figure 37. 4-Wire
CS
Mode Serial Interface Timing