Datasheet

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16-Bit Lower Power

PulSAR ADCs in MSOP/LFCSP (QFN)

Data Sheet

AD7988-1/AD7988-5

Rev. D Document Feedback

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FEATURES

Low power dissipation

AD7988-1

400 µW at 100 kSPS (VDD only)

700 µW at 100 kSPS (total)

AD7988-5

2 mW at 500 kSPS (VDD only)

3.5 mW at 500 kSPS (total)

16-bit resolution with no missing codes

Throughput: 100 kSPS/500 kSPS options

INL: ±0.6 LSB typical, ±1.25 LSB maximum

SINAD: 91.5 dB at 10 kHz

THD: −114 dB at 10 kHz

Pseudo differential analog input range

0 V to V

REF

with V

REF

from 2.5 V to 5.5 V

Any input range and easy to drive with the ADA4841-1

No pipeline delay

Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V logic

interface

SPI-/QSPI-/MICROWIRE™-/DSP-compatible serial interface

Daisy-chain multiple ADCs

10-lead MSOP and 10-lead, 3 mm × 3 mm LFCSP (QFN), same

space as SOT-23

Wide operating temperature range: −40°C to +125°C

APPLICATIONS

Battery-powered equipment

Low power data acquisition systems

Portable medical instruments

ATE equipment

Data acquisitions

Communications

GENERAL DESCRIPTION

The AD7988-1/AD7988-5 are 16-bit, successive approximation,

analog-to-digital converters (ADC) that operate from a single

power supply, VDD. The AD7988-1 offers a 100 kSPS throughput,

and the AD7988-5 offers a 500 kSPS throughput. They are low

power, 16-bit sampling ADCs with a versatile serial interface

port. On the CNV rising edge, they sample an analog input,

IN+, between 0 V to V

REF

with respect to a ground sense, IN−.

The reference voltage, REF, is applied externally and can be set

independent of the supply voltage, VDD.

The SPI-compatible serial interface also features the ability to

daisy-chain several ADCs on a single 3-wire bus using the SDI

input. It is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic using

the separate supply, VIO.

The AD7988-1/AD7988-5 generics are housed in a 10-lead

MSOP or a 10-lead LFCSP (QFN) with operation specified

from −40°C to +125°C.

Table 1. MSOP, LFCSP (QFN) 14-/16-/18-Bit PulSAR® ADCs

Bits 100 kSPS 250 kSPS

400 kSPS to

500 kSPS

≥1000

kSPS

ADC Driver

AD7691

AD7690

AD7982

ADA4941-1

AD7984

ADA4841-1

AD7684 AD7687

AD7688

ADA4941-1

AD7693

ADA4841-1

AD7680 AD7685

AD7686

AD7980

ADA4841-1

AD7683 AD7694 AD7988-5

AD7988-1

AD7940 AD7942

AD7946

ADA4841-1

True differential.

Pin-for-pin compatible.

Pseudo differential.

TYPICAL APPLICATION DIAGRAM

REF

GND

VDD

IN+

IN–

VIO

SDI

SCK

SDO

CNV

1.8V TO 5.5V

3- OR 4-WIRE INTERFACE

(SPI, DAISY CHAIN, CS)

2.5V TO 5V 2.5V

0V T

O V

REF

10231-001

AD7988-1/

AD7988-5

Figure 1.

Summary of content (24 pages)

PAGE 1
6-Bit Lower Power PulSAR ADCs in MSOP/LFCSP (QFN) AD7988-1/AD7988-5 Data Sheet FEATURES GENERAL DESCRIPTION Low power dissipation AD7988-1 400 µW at 100 kSPS (VDD only) 700 µW at 100 kSPS (total) AD7988-5 2 mW at 500 kSPS (VDD only) 3.5 mW at 500 kSPS (total) 16-bit resolution with no missing codes Throughput: 100 kSPS/500 kSPS options INL: ±0.6 LSB typical, ±1.25 LSB maximum SINAD: 91.5 dB at 10 kHz THD: −114 dB at 10 kHz Pseudo differential analog input range 0 V to VREF with VREF from 2.5 V to 5.
PAGE 2
AD7988-1/AD7988-5 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analog Inputs ............................................................................. 16 Applications ....................................................................................... 1 Driver Amplifier Choice ........................................................... 16 General Description ................................................
PAGE 3
Data Sheet AD7988-1/AD7988-5 SPECIFICATIONS VDD = 2.5 V, VIO = 2.3 V to 5.5 V, VREF = 5 V, TA = –40°C to +125°C, unless otherwise noted. Table 2.
PAGE 4
AD7988-1/AD7988-5 Data Sheet VDD = 2.5 V, VIO = 2.3 V to 5.5 V, VREF = 5 V, TA = –40°C to +125°C, unless otherwise noted. Table 3. Parameter REFERENCE Voltage Range Load Current SAMPLING DYNAMICS −3 dB Input Bandwidth Aperture Delay DIGITAL INPUTS Logic Levels VIL VIH VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Pipeline Delay VOL VOH POWER SUPPLIES VDD VIO VIO Range Standby Current 1, 2 AD7988-1 Power Dissipation Total Test Conditions/Comments Min Typ 2.4 Max Unit 5.
PAGE 5
Data Sheet AD7988-1/AD7988-5 TIMING SPECIFICATIONS VDD = 2.37 V to 2.63 V, VIO = 3.3 V to 5.5 V, −40°C to +125°C unless otherwise stated. See Figure 2 and Figure 3 for load conditions. Table 4. Parameter AD7988-1 Throughput Rate Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions AD7988-5 Throughput Rate Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions CNV Pulse Width (CS Mode) SCK Period (CS Mode) VIO Above 4.
PAGE 6
AD7988-1/AD7988-5 Data Sheet 500µA IOL 1.4V TO SDO 500µA 10231-002 CL 20pF IOH Figure 2. Load Circuit for Digital Interface Timing Y% VIO1 X% VIO1 tDELAY VIH2 VIL2 VIH2 VIL2 1FOR VIO ≤ 3.0V, X = 90 AND Y = 10; FOR VIO > 3.0V X = 70, AND Y = 30. 2MINIMUM V AND MAXIMUM V USED. SEE DIGITAL INPUTS IH IL SPECIFICATIONS IN TABLE 3. Figure 3. Voltage Levels for Timing Rev.
PAGE 7
Data Sheet AD7988-1/AD7988-5 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Analog Inputs IN+, 1 IN−1 to GND Supply Voltage REF, VIO to GND VDD to GND VDD to VIO Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature θJA Thermal Impedance 10-Lead MSOP 10-Lead LFCSP θJC Thermal Impedance 10-Lead MSOP 10-Lead LFCSP Reflow Soldering 1 Rating −0.3 V to VREF + 0.3 V or ±130 mA −0.3 V to +6 V −0.3 V to +3 V +3 V to −6 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.
PAGE 8
AD7988-1/AD7988-5 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS REF 1 10 VIO 9 SDI IN+ 3 AD7988-1/ AD7988-5 8 SCK IN– 4 TOP VIEW (Not to Scale) 7 SDO 6 CNV VDD 2 GND 5 IN– 4 GND 5 10231-004 REF 1 IN+ 3 10 VIO AD7988-1/ AD7988-5 9 TOP VIEW (Not to Scale) 8 SCK 7 SDO 6 CNV SDI NOTES 1. THE EXPOSED PAD CAN BE CONNECTED TO GND. Figure 4. 10-Lead MSOP Pin Configuration 10231-005 VDD 2 Figure 5. 10-Lead LFCSP Pin Configuration Table 6.
PAGE 9
Data Sheet AD7988-1/AD7988-5 TERMINOLOGY Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 30).
PAGE 10
AD7988-1/AD7988-5 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VDD = 2.5 V, VREF = 5.0 V, VIO = 3.3 V, unless otherwise noted. 0 0 fS = 500kSPS fIN = 10kHz SNR = 91.17dB THD = –113.63dB SFDR = 110.30dB SINAD = 91.15dB –40 –60 –80 –100 –120 –140 –160 –60 –80 –100 –120 –140 100 150 200 250 FREQUENCY (kHz) –180 0 10 20 30 Figure 6. AD7988-5 FFT Plot, VREF = 5 V 1.25 fS = 500kSPS fIN = 10kHz 0.75 0.50 INL (LSB) –60 POSITIVE INL: +0.40 LSB NEGATIVE INL: –0.35 LSB 1.00 SNR = 86.
PAGE 11
Data Sheet AD7988-1/AD7988-5 1.00 60k POSITIVE INL: +0.18 LSB NEGATIVE INL: –0.21 LSB 0.75 50970 50k 45198 0.50 40k COUNTS DNL (LSB) 0.25 0 30k –0.25 18848 20k –0.50 12424 10k –0.75 65536 CODE 1217 2290 30 0 0 Figure 15. Histogram of a DC Input at the Code Transition, VREF = 2.5 V 16 100 SNR SINAD ENOB SNR, SINAD (dB) 0.50 0.25 DNL (LSB) 94 CODE IN HEX POSITIVE INL: +0.25 LSB NEGATIVE INL: –0.22 LSB 0.
PAGE 12
AD7988-1/AD7988-5 Data Sheet 95 95 94 93 93 92 SNR (dB) SNR (dB) 91 90 89 91 89 88 87 87 –8 –7 –6 –5 –4 –3 –2 –1 0 INPUT LEVEL (dB OF FULL SCALE) 85 –55 –35 –15 5 25 45 65 85 105 125 10231-053 –9 10231-018 85 –10 2.625 10231-023 86 TEMPERATURE (°C) Figure 21. SNR vs. Temperature Figure 18. SNR vs. Input Level –95 115 0.7 IVDD –100 0.6 110 SFDR 100 THD –115 CURRENT (mA) –110 SFDR (dB) 105 95 0.4 0.3 IREF 0.2 IVIO 90 –125 2.25 2.75 3.25 3.75 4.
PAGE 13
Data Sheet AD7988-1/AD7988-5 –85 0.14 –90 0.12 IVDD –95 CURRENT (mA) 0.10 THD (dB) –100 –105 –110 008 0.06 IREF 0.04 –115 IVIO 1k 100 FREQUENCY (kHz) 0 –55 10231-054 –125 10 –35 –15 5 25 45 65 85 105 10231-028 0.02 –120 125 TEMPERATURE (°C) Figure 24. THD vs. Frequency Figure 27. Operating Currents vs. Temperature (AD7988-1) 8 –110 7 –112 CURRENT (µA) THD (dB) 6 –114 –116 5 4 3 IVDD + IVIO 2 –118 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) Figure 25.
PAGE 14
AD7988-1/AD7988-5 Data Sheet THEORY OF OPERATION IN+ MSB LSB 32,768C 16,384C 4C 2C C SWITCHES CONTROL SW+ C BUSY REF COMP GND 32,768C 16,384C 4C 2C C CONTROL LOGIC OUTPUT CODE C LSB MSB SW– 10231-030 CNV IN– Figure 29. ADC Simplified Schematic CIRCUIT INFORMATION The AD7988-1/AD7988-5 devices are fast, low power, singlesupply, precise 16-bit ADCs that use a successive approximation architecture.
PAGE 15
Data Sheet AD7988-1/AD7988-5 Transfer Functions Table 7. Output Codes and Ideal Input Voltages The ideal transfer characteristic for the AD7988-x is shown in Figure 30 and Table 7. Description FSR – 1 LSB Midscale + 1 LSB Midscale Midscale – 1 LSB –FSR + 1 LSB –FSR 111 ... 101 1 2 Analog Input Digital Output Code (Hex) FFFF1 8001 8000 7FFF 0001 00002 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND).
PAGE 16
AD7988-1/AD7988-5 Data Sheet ANALOG INPUTS DRIVER AMPLIFIER CHOICE Figure 32 shows an equivalent circuit of the input structure of the AD7988-x. Although the AD7988-x is easy to drive, the driver amplifier needs to meet the following requirements: The two diodes, D1 and D2, provide ESD protection for the analog inputs, IN+ and IN−. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.
PAGE 17
Data Sheet AD7988-1/AD7988-5 VOLTAGE REFERENCE INPUT The AD7988-x voltage reference input, REF, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the REF and GND pins, as explained in the Layout section. When REF is driven by a very low impedance source, for example, a reference buffer using the AD8031 or the AD8605, a ceramic chip capacitor is appropriate for optimum performance.
PAGE 18
AD7988-1/AD7988-5 Data Sheet CS MODE, 3-WIRE When CNV goes low, the MSB is output onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided that it has an acceptable hold time. After the 16th SCK falling edge or when CNV goes high, whichever is earlier, SDO returns to high impedance.
PAGE 19
Data Sheet AD7988-1/AD7988-5 When the conversion is complete, the AD7988-x enters the acquisition phase and powers down. Each ADC result can be read by bringing its SDI input low, which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided that it has an acceptable hold time.
PAGE 20
AD7988-1/AD7988-5 Data Sheet phase and the subsequent data readback. When the conversion is complete, the MSB is output onto SDO and the AD7988-x enters the acquisition phase and powers down. The remaining data bits stored in the internal shift register are clocked by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 16 × N clocks are required to read back the N ADCs.
PAGE 21
Data Sheet AD7988-1/AD7988-5 APPLICATIONS INFORMATION INTERFACING TO BLACKFIN® DSP The AD7988-x can easily connect to a DSP SPI or SPORT. The SPI configuration is straightforward, using the standard SPI interface as shown in Figure 40. SPI_CLK SCK SPI_MISO SDO SPI_MOSI CNV AD7988-1/ AD7988-5 10231-041 BLACKFIN DSP Figure 40. Typical Connection to Blackfin SPI Interface Similarly, the SPORT interface can be used to interface to this ADC.
PAGE 22
AD7988-1/AD7988-5 Data Sheet OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 0.70 0.55 0.40 0.23 0.13 6° 0° 091709-A 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 44.10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 2.48 2.38 2.23 3.10 3.00 SQ 2.90 0.50 BSC 10 6 1.74 1.64 1.49 EXPOSED PAD 0.50 0.40 0.
PAGE 23
Data Sheet AD7988-1/AD7988-5 ORDERING GUIDE Model 1 AD7988-1BRMZ AD7988-1BRMZ-RL7 AD7988-1BCPZ-RL AD7988-1BCPZ-RL7 AD7988-5BRMZ AD7988-5BRMZ-RL7 AD7988-5BCPZ-RL AD7988-5BCPZ-RL7 EVAL-AD7988-5SDZ Notes EVAL-SDP-CB1Z 3 2 Integral Nonlinearity ±1.25 LSB max ±1.25 LSB max ±1.25 LSB max ±1.25 LSB max ±1.25 LSB max ±1.25 LSB max ±1.25 LSB max ±1.