Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal LFCSP 20 VQ

18-Bit, 2 MSPS PulSAR

15 mW ADC in LFCSP (QFN)

AD7986

Rev. B

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FEATURES

18-bit resolution with no missing codes

Throughput: 2 MSPS (TURBO = high), 1.5 MSPS (TURBO = low)

Low power dissipation

15 mW at 2 MSPS, with external reference

26 mW at 2 MSPS with internal reference

INL: ±1 LSB typical, ±2.5 LSB maximum

SNR

95.5 dB, with on-chip reference

97.0 dB, with external reference

4.096 V internal reference: typical drift of 10 ppm/°C

True differential analog input voltage range: ±V

REF

0 V to V

REF

with V

REF

up to 5.0 V

Allows use of any input range

No pipeline delay

Logic interface: 1.8 V/2.5 V/2.7 V

Serial interface: SPI/QSPI™/MICROWIRE™/DSP compatible

Ability to daisy-chain multiple ADCs with busy indicator

20-lead 4 mm × 4 mm LFCSP (QFN)

APPLICATIONS

Battery-powered equipment

Data acquisition systems

Medical instruments

Seismic data acquisition systems

APPLICATION DIAGRAM

2.7nF

15Ω

V–

REF

NOTES

1. GND REFERS TO REFGND, AGND, AND DGND.

V+

2.7nF

15Ω

V–

V+

IN–

AD7986

IN+

REF

AVDD,

DVDD

VIO

BVDD

5V 2.5V

1.8

2.7V

VIO

SDI

SCK

SDO

CNV

3- OR 4-WIRE

INTERFACE:

SPI, CS

DAISY CHAIN

(TURBO = LOW)

TURBO

10µF

REF

GND

07956-001

Figure 1.

GENERAL DESCRIPTION

The AD7986 is an 18-bit, 2 MSPS successive approximation,

analog-to-digital converter (ADC). It contains a low power,

high speed, 18-bit sampling ADC, an internal conversion clock,

an internal reference (and buffer), error correction circuits, and

a versatile serial interface port. On the rising edge of CNV, the

AD7986 samples the voltage difference between the IN+ and

IN− pins. The voltages on these pins usually swing in opposite

phases between 0 V and V

REF

. It features a very high sampling

rate turbo mode (TURBO = high) and a reduced power normal

mode (TURBO = low) for low power applications where the

power is scaled with the throughput.

In normal mode (TURBO = low), the SPI-compatible serial

interface also features the ability, using the SDI input, to daisy-

chain several ADCs on a single 3-wire bus and provide an

optional busy indicator. It is compatible with 1.8 V, 2.5 V, and 2.7 V

using the separate VIO supply.

The AD7986 is available in a 20-lead LFCSP (QFN) with

operation specified from −40°C to +85°C.

Table 1. MSOP, LFCSP (QFN) 14-/16-/18-Bit PulSAR® ADCs

Type 100 kSPS 250 kSPS 400 kSPS to 500 kSPS ≥1000 kSPS ADC Driver

14-Bit AD7940 AD7942

AD7946

16-Bit AD7680

AD7685

AD7686

AD7980

ADA4941-1

AD7683

AD7687

AD7688

AD7983

ADA4841-x

AD7684 AD7694

AD7693

18-Bit

AD7691

AD7690

AD7982

ADA4941-1

AD7984

ADA4841-x

AD7986 AD8021

Pin-for-pin compatible.

Summary of content (28 pages)

PAGE 1
8-Bit, 2 MSPS PulSAR 15 mW ADC in LFCSP (QFN) AD7986 FEATURES APPLICATION DIAGRAM 18-bit resolution with no missing codes Throughput: 2 MSPS (TURBO = high), 1.5 MSPS (TURBO = low) Low power dissipation 15 mW at 2 MSPS, with external reference 26 mW at 2 MSPS with internal reference INL: ±1 LSB typical, ±2.5 LSB maximum SNR 95.5 dB, with on-chip reference 97.0 dB, with external reference 4.
PAGE 2
AD7986 TABLE OF CONTENTS Features .............................................................................................. 1 Analog Inputs.............................................................................. 15 Applications ....................................................................................... 1 Driver Amplifier Choice ........................................................... 15 Application Diagram ........................................................................
PAGE 3
AD7986 SPECIFICATIONS AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, VREF = 4.096 V, TA = −40°C to +85°C, unless otherwise noted. Table 2.
PAGE 4
AD7986 AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, VREF = 4.096 V, TA = −40°C to +85°C, unless otherwise noted. Table 3.
PAGE 5
AD7986 TIMING SPECIFICATIONS AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, VREF = 4.096 V, TA = −40°C to +85°C, unless otherwise noted.1 Table 4.
PAGE 6
AD7986 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Analog Inputs IN+, IN− to GND 1 Supply Voltage REF, BVDD to GND, REFGND AVDD, DVDD, VIO to GND AVDD and DVDD to VIO Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature θJA Thermal Impedance 20-Lead LFCSP (QFN) Lead Temperatures Vapor Phase (60 sec) Infrared (15 sec) 1 Rating −0.3 V to VREF + 0.3 V or ±130 mA −0.3 V to +6.0 V −0.3 V to +2.7 V +3 V to −6 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.
PAGE 7
AD7986 1 2 3 4 5 PIN 1 INDICATOR AD7986 TOP VIEW (Not to Scale) 15 TURBO 14 SDI 13 CNV 12 SCK 11 DVDD IN+ PDREF VIO SDO DGND 6 7 8 9 10 REF REF REFGND REFGND IN– 07956-004 20 19 18 17 16 REFIN BVDD AGND AGND AVDD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NOTES 1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SYSTEM GROUND PLANE. Figure 4. Pin Configuration Table 6.
PAGE 8
AD7986 Pin No. 16 17,18 19 Mnemonic AVDD AGND BVDD Type1 P P P 20 REFIN AI/O 21 (EPAD) Exposed Pad EP 1 Description Input Analog Power. Nominally at 2.5 V. Analog Power Ground. Reference buffer power. Nominally 5.0 V. If an external reference buffer is used to achieve the maximum SNR performance with 5 V reference, the reference buffer must be powered down by connecting the REFIN pin to ground. The external reference buffer must be connected to the BVDD pin.
PAGE 9
AD7986 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = DVDD = VIO = 2.5 V, BVDD = 5.0 V, VREF = 5.0 V, external reference (PDREF = high, REFIN = low), unless otherwise noted. 2.5 2.0 POSITIVE INL = +1.57LSB NEGATIVE INL = –1.25LSB 2.0 POSITIVE DNL = +0.54LSB NEGATIVE DNL = –0.60LSB 1.5 1.5 1.0 0.5 DNL (LSB) INL (LSB) 1.0 0 –0.5 0.5 0 –0.5 –1.0 –1.0 –1.5 –2.5 0 65,536 131,072 CODE 196,608 07956-008 –1.5 07956-005 –2.0 –2.0 0 262,144 65,536 Figure 5. Integral Nonlinearity vs.
PAGE 10
AD7986 0 0 fS = 2MSPS fIN = 20kHz SNR = 97.0dB THD = –114.0dB SINAD = 97.0dB –20 –40 –40 AMPLITUDE (dB) –80 –100 –120 –140 –60 –80 –100 –120 –140 07956-111 –160 –180 –200 0 200k 400k 600k FREQUENCY (Hz) 800k 07956-114 AMPLITUDE (dB) –60 fS = 2MSPS fIN = 20kHz SNR = 95.5dB THD = –113.0dB SINAD = 95.5dB –20 –160 –180 1M 0 Figure 11. FFT Plot (External Reference) 200k 400k 600k FREQUENCY (Hz) 800k 1M Figure 14.
PAGE 11
AD7986 3.0 99 IREF 2.5 97 96 95 94 93 92 2.0 IAVDD 1.5 1.0 0.5 IBVDD 91 –9 –8 –7 –6 –5 –4 INPUT LEVEL (dB) –3 –2 –1 0 0 –55 07956-032 90 –10 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (C) Figure 17. SNR vs. Input Level 07956-034 98 SUPPLY CURRENT (mA) SNR (dB REFERRED TO FULL SCALE) 100 Figure 19. Operating Currents vs. Temperature 3.0 14 IREF 12 SUPPLY CURRENT (µA) 2.0 IAVDD IDVDD 1.0 8 6 4 IAVDD + IDVDD + IVIO IBVDD 0.5 2 IVIO 0 2.375 10 2.425 2.475 2.
PAGE 12
AD7986 TERMINOLOGY Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 22).
PAGE 13
AD7986 THEORY OF OPERATION IN+ SWITCHES CONTROL LSB MSB REF 131,072C 65,536C 4C 2C C SW+ C BUSY COMP REFGND 131,072C 65,536C 4C 2C C C OUTPUT CODE LSB MSB CONTROL LOGIC SW– 07956-011 CNV IN– Figure 21. ADC Simplified Schematic CIRCUIT INFORMATION The AD7986 is a fast, low power, single-supply, precise, 18-bit ADC using a successive approximation architecture. The AD7986 features different modes to optimize performance according to the application.
PAGE 14
AD7986 Transfer Functions Table 7. Output Codes and Ideal Input Voltages Description FSR − 1 LSB Midscale + 1 LSB Midscale Midscale − 1 LSB −FSR + 1 LSB −FSR 011 ... 111 011 ... 110 011 ... 101 1 2 100 ... 010 Analog Input VREF = 5 V +4.095969 V +31.25 µV 0V −31.25 µV −4.095969 V −4.096 V Digital Output Code (Hex) 0x1FFFF1 0x00001 0x00000 0x3FFFF 0x20001 0x200002 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − REFGND).
PAGE 15
AD7986 ANALOG INPUTS DRIVER AMPLIFIER CHOICE Figure 24 shows an equivalent circuit of the input structure of the AD7986. Although the AD7986 is easy to drive, the driver amplifier must meet the following requirements: The two diodes, D1 and D2, provide ESD protection for the analog inputs, IN+ and IN−. Care must be taken to ensure that the analog input signal does not exceed the reference input voltage (REF) by more than 0.3 V.
PAGE 16
AD7986 VOLTAGE REFERENCE INPUT The advantages of directly using the external voltage reference are: The AD7986 allows the choice of a very low temperature drift internal voltage reference, an external reference, or an external buffered reference. • The internal reference of the AD7986 provides excellent performance and can be used in almost all applications. The SNR and dynamic range improvement (about 1.7 dB) resulting from the use of a larger reference voltage (5 V) instead of a typical 4.
PAGE 17
AD7986 DIGITAL INTERFACE Although the AD7986 has a reduced number of pins, it offers flexibility in its serial interface modes. When in CS mode, the AD7986 is compatible with SPI, MICROWIRE™, QSPI™, and digital hosts. In this mode, the AD7986 can use either a 3-wire or a 4-wire interface. A 3-wire interface using the CNV, SCK, and SDO signals minimizes wiring connections, which is useful, for instance, in isolated applications.
PAGE 18
AD7986 DATA READING OPTIONS There are three different data reading options for the AD7986. There is the option to read during conversion, to split the read across acquisition and conversion (see Figure 27 and Figure 28), and in normal mode, to read during acquisition. The desired SCK frequency largely determines which reading option to pursue.
PAGE 19
AD7986 CS MODE, 3-WIRE WITHOUT BUSY INDICATOR conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. When the conversion is complete, the AD7986 enters the acquisition phase and powers down. When CNV goes low, the MSB is output onto SDO. The remaining data bits are clocked by subsequent SCK falling edges. The data is valid on both SCK edges.
PAGE 20
AD7986 CS MODE, 3-WIRE WITH BUSY INDICATOR When the conversion is complete, SDO goes from high impedance to low impedance. With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. The AD7986 then enters the acquisition phase and powers down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges.
PAGE 21
AD7986 CS MODE, 4-WIRE WITHOUT BUSY INDICATOR but SDI must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. When the conversion is complete, the AD7986 enters the acquisition phase and powers down. Each ADC result can be read by bringing its SDI input low, which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges.
PAGE 22
AD7986 CS MODE, 4-WIRE WITH BUSY INDICATOR used to select other SPI devices, such as analog multiplexers, but SDI must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. When the conversion is complete, SDO goes from high impedance to low impedance.
PAGE 23
AD7986 CHAIN MODE WITHOUT BUSY INDICATOR held high during the conversion phase and the subsequent data readback. When the conversion is complete, the MSB is output onto SDO, and the AD7986 enters the acquisition phase and powers down. The remaining data bits stored in the internal shift register are clocked by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge.
PAGE 24
AD7986 CHAIN MODE WITH BUSY INDICATOR subsequent data readback. When all ADCs in the chain have completed their conversions, the SDO pin of the ADC closest to the digital host (see the AD7986 ADC labeled C in Figure 35) is driven high. This transition on SDO can be used as a busy indicator to trigger the data readback controlled by the digital host. The AD7986 then enters the acquisition phase and powers down.
PAGE 25
AD7986 APPLICATION HINTS LAYOUT The printed circuit board (PCB) that houses the AD7986 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7986, with its analog signals on the left side and its digital signals on the right side, eases this task. Avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the AD7986 is used as a shield.
PAGE 26
AD7986 AVDD BVDD REF REF REF PADDLE 1 2 GND GND GND GND 3 4 DVDD 5 GND 6 GND 07956-030 GND VIO Figure 37. Example Layout of the AD7986 (Top Layer) 5V EXTERNAL REFERENCE (ADR435 OR ADR445) REF REF AVDD CAVDD CBVDD BVDD REF GND CREF GND GND GND GND CDVDD DVDD GND GND VIO CVIO VIO 07956-031 GND Figure 38. Example Layout of the AD7986 (Bottom Layer) Rev.
PAGE 27
AD7986 OUTLINE DIMENSIONS 0.60 MAX 4.00 BSC SQ 0.60 MAX 15 PIN 1 INDICATOR 20 16 1 PIN 1 INDICATOR 3.75 BSC SQ 0.50 BSC 2.65 2.50 SQ 2.35 EXPOSED PAD (BOTTOM VIEW) 5 10 1.00 0.85 0.80 12° MAX SEATING PLANE 0.50 0.40 0.30 0.80 MAX 0.65 TYP 0.30 0.23 0.18 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.