Datasheet

AD7985
Rev. A | Page 5 of 28
TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, V
REF
= 4.096 V, T
A
= −40°C to +85°C, unless otherwise noted.
1
Table 4.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
Conversion Time: CNV Rising Edge
to Data Available
t
CONV
Turbo mode/normal mode 320/420 ns
Acquisition Time t
ACQ
80 ns
Time Between Conversions t
CYC
Turbo mode/normal mode 400/500 ns
CNV Pulse Width t
CNVH
CS
mode 10 ns
Data Read During Conversion t
DATA
Turbo mode/normal mode 190/290 ns
Quiet Time During Acquisition from Last SCK
Falling Edge to CNV Rising Edge
t
QUIET
20 ns
SCK Period t
SCK
CS
mode 9 ns
t
SCK
Chain mode 11 ns
SCK Low Time t
SCKL
3.5 ns
SCK High Time t
SCKH
3.5 ns
SCK Falling Edge to Data Remains Valid t
HSDO
2 ns
SCK Falling Edge to Data Valid Delay t
DSDO
4 ns
CNV or SDI Low to SDO D15 MSB Valid t
EN
5 ns
CNV or SDI High or Last SCK Falling Edge
to SDO High Impedance
t
DIS
CS
mode 8 ns
SDI Valid Setup Time from CNV Rising Edge t
SSDICNV
4 ns
SDI Valid Hold Time from CNV Rising Edge t
HSDICNV
CS
mode 0 ns
t
HSDICNV
Chain mode 0 ns
SCK Valid Setup Time from CNV Rising Edge t
SSCKCNV
Chain mode 5 ns
SCK Valid Hold Time from CNV Rising Edge t
HSCKCNV
Chain mode 5 ns
SDI Valid Setup Time from SCK Falling Edge t
SSDISCK
Chain mode 2 ns
SDI Valid Hold Time from SCK Falling Edge t
HSDISCK
Chain mode 3 ns
SDI High to SDO High t
DSDOSDI
Chain mode with busy indicator 15 ns
1
See Figure 2 and Figure 3 for load conditions.
500µA I
OL
500µA I
OH
1.4V
TO SDO
C
L
20pF
07947-002
Figure 2. Load Circuit for Digital Interface Timing
90% VIO
10% VIO
V
IH
1
V
IL
1
V
IL
1
V
IH
1
t
DELAY
t
DELAY
1
MINIMUM V
IH
AND MAXIMUM V
IL
USED. SEE DIGITAL INPUTS
SPECIFICATIONS IN TABLE 3.
07947-003
Figure 3. Voltage Levels for Timing