Datasheet

AD7984

Rev. A | Page 16 of 24

DIGITAL INTERFACE

Although the AD7984 has a reduced number of pins, it offers

flexibility in its serial interface modes.

When in

mode, the AD7984 is compatible with SPI, QSPI,

digital hosts, and DSPs. In this mode, the AD7984 can use

either a 3-wire or 4-wire interface. A 3-wire interface using the

CNV, SCK, and SDO signals minimizes wiring connections

useful, for instance, in isolated applications. A 4-wire interface

using the SDI, CNV, SCK, and SDO signals allows CNV, which

initiates the conversions, to be independent of the readback

timing (SDI). This is useful in low jitter sampling or

simultaneous sampling applications.

When in chain mode, the AD7984 provides a daisy-chain feature

using the SDI input for cascading multiple ADCs on a single

data line similar to a shift register.

The mode in which the part operates depends on the SDI level

when the CNV rising edge occurs. The

mode is selected if

SDI is high, and the chain mode is selected if SDI is low. The

SDI hold time is such that when SDI and CNV are connected,

the chain mode is always selected.

In either mode, the AD7984 offers the option of forcing a start

bit in front of the data bits. This start bit can be used as a busy

signal indicator to interrupt the digital host and trigger the data

reading. Otherwise, without a busy indicator, the user must timeout

the maximum conversion time prior to readback.

The busy indicator feature is enabled

• In

mode if CNV or SDI is low when the ADC

conversion ends (see and ). Figure 31 Figure 35

• In chain mode if SCK is high during the CNV rising edge

(see Figure 39).