Datasheet

AD7984
Rev. A | Page 23 of 24
APPLICATION HINTS
LAYOUT
The printed circuit board (PCB) that houses the AD7984
should be designed so that the analog and digital sections are
separated and confined to certain areas of the board. The
pinout of the AD7984, with its analog signals on the left side
and its digital signals on the right side, eases this task.
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7984 is used as a shield. Fast switching signals, such as CNV
or clocks, should not run near analog signal paths. Crossover of
digital and analog signals should be avoided.
At least one ground plane should be used. It can be common or
split between the digital and analog sections. In the latter case,
the planes should be joined underneath the AD7984.
The AD7984 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, ideally right up against, the REF and
GND pins and connecting them with wide, low impedance traces.
Finally, the power supplies VDD and VIO of the AD7984
should be decoupled with ceramic capacitors, typically 100 nF,
placed close to the AD7984 and connected using short, wide
traces to provide low impedance paths and to reduce the effect
of glitches on the power supply lines.
An example of layout following these rules is shown in
Figure 40 and Figure 41.
EVALUATING THE AD7984 PERFORMANCE
Other recommended layouts for the AD7984 are outlined
in the documentation of the evaluation board for the AD7984
(EVAL-AD7984CBZ). The evaluation board package includes
a fully assembled and tested evaluation board, documentation,
and software for controlling the board from a PC via the
EVAL-CONTROL BRD3Z.
AD7984
06973-030
Figure 40. Example Layout of the AD7984 (Top Layer)
06973-031
Figure 41. Example Layout of the AD7984 (Bottom Layer)