Datasheet

AD7984
Rev. A | Page 20 of 24
CS MODE, 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7984 is connected
to an SPI-compatible digital host with an interrupt input and
when it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This independence is particularly important in
applications where low jitter on CNV is desired.
The connection diagram is shown in Figure 34, and the
corresponding timing is given in Figure 35.
With SDI high, a rising edge on CNV initiates a conversion,
selects the
CS
mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time elapses and then held low for the maximum possible
conversion time to guarantee the generation of the busy signal
indicator. When the conversion is complete, SDO goes from
high impedance to low impedance. With a pull-up on the SDO
line, this transition can be used as an interrupt signal to initiate
the data readback controlled by the digital host. The AD7984
then enters the acquisition phase and goes into standby mode.
The data bits are then clocked out, MSB first, by subsequent
SCK falling edges. The data is valid on both SCK edges. Although
the rising edge can be used to capture the data, a digital host
using the SCK falling edge allows a faster reading rate, provided
it has an acceptable hold time. After the optional 19
th
SCK
falling edge or SDI going high (whichever occurs first), SDO
returns to high impedance.
AD7984
SDI SDO
CNV
SCK
CONVERT
DATA IN
CLK
DIGITAL HOST
IRQ
VIO
47kΩ
CS1
06973-024
Figure 34.
CS
Mode, 4-Wire with Busy Indicator Connection Diagram
SDO
D17 D16 D1 D0
t
DIS
SCK
1 2 3 171819
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
t
EN
CONVERSIONACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
SDI
CNV
t
SSDICNV
t
HSDICNV
06973-025
Figure 35.
CS
Mode, 4-Wire with Busy Indicator Serial Interface Timing