Datasheet

AD7984
Rev. A | Page 17 of 24
CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when a single AD7984 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 28, and the corresponding timing is given in
Figure 29.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the
CS
mode, and forces SDO to high
impedance. When a conversion is initiated, it continues until
completion irrespective of the state of CNV. This can be useful,
for example, to bring CNV low to select other SPI devices, such
as analog multiplexers; however, CNV must be returned high
before the minimum conversion time elapses and then held
high for the maximum possible conversion time to avoid the
generation of the busy signal indicator. When the conversion is
complete, the AD7984 enters the acquisition phase and goes
into standby mode. When CNV goes low, the MSB is output
onto SDO. The remaining data bits are clocked by subsequent
SCK falling edges. The data is valid on both SCK edges. Although
the rising edge can be used to capture the data, a digital host
using the SCK falling edge allows a faster reading rate, provided
it has an acceptable hold time. After the 18
th
SCK falling edge or
when CNV goes high (whichever occurs first), SDO returns to
high impedance.
AD7984
SDI SDO
CNV
SCK
CONVERT
DATA IN
CLK
DIGITAL HOST
VIO
06973-018
Figure 28.
CS
Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High)
SDO
D17 D16 D15 D1 D0
t
DIS
SCK
1 2 3 16 17 18
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
CNV
CONVERSIONACQUISITION
t
CONV
t
CYC
ACQUISITION
SDI = 1
t
CNVH
t
ACQ
t
EN
06973-019
Figure 29.
CS
Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)