Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External LFCSP 10 WD

18-Bit, 1.33 MSPS PulSAR 10.5 mW

ADC in MSOP/QFN

AD7984

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

18-bit resolution with no missing codes

Throughput: 1.33 MSPS

Low power dissipation: 10.5 mW at 1.33 MSPS

INL: ±2.25 LSB maximum

Dynamic range: 99.7 dB typical

True differential analog input range: ±V

REF

0 V to V

REF

with V

REF

between 2.9 V to 5.0 V

Allows use of any input range

Easy to drive with the ADA4941

No pipeline delay

Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V logic

interface

Serial interface SPI-/QSPI™-/MICROWIRE™-/DSP-compatible

Ability to daisy-chain multiple ADCs and busy indicator

10-lead MSOP (MSOP-8 size) and 10-lead 3 mm × 3 mm QFN

(LFCSP), SOT-23 size

APPLICATIONS

Battery-powered equipment

Data acquisition systems

Medical instruments

Seismic data acquisition systems

APPLICATION DIAGRAM

AD7984

REF

GND

VDD

IN+

IN–

VIO

SDI

SCK

SDO

CNV

1.8V TO 5V

ADA4941

3- OR 4-WIRE

INTERFACE

(SPI, CS

DAISY CHAIN)

2.9V TO 5

2.5

10V, ±5V, ..

06973-001

Figure 1.

GENERAL DESCRIPTION

The AD7984 is an 18-bit, successive approximation, analog-to-

digital converter (ADC) that operates from a single power

supply, VDD. It contains a low power, high speed, 18-bit

sampling ADC and a versatile serial interface port. On the CNV

rising edge, the AD7984 samples the voltage difference between

the IN+ and IN− pins. The voltages on these pins usually swing

in opposite phases between 0 V and V

REF

. The reference voltage,

REF, is applied externally and can be set independent of the

supply voltage, VDD.

The SPI-compatible serial interface also features the ability,

using the SDI input, to daisy-chain several ADCs on a single

3-wire bus and provides an optional busy indicator. It is compatible

with 1.8 V, 2.5 V, 3 V, and 5 V logic, using the separate VIO supply.

The AD7984 is available in a 10-lead MSOP or a 10-lead QFN

(LFCSP) with operation specified from −40°C to +85°C.

Table 1. MSOP, QFN (LFCSP) 14-/16-/18-Bit PulSAR® ADC

Type 100 kSPS 250 kSPS 400 kSPS to 500 kSPS ≥1000 kSPS ADC Driver

14-Bit AD7940 AD7942

AD7946

16-Bit AD7680 AD7685

AD7686

AD7980

ADA4941-x

AD7683 AD7687

AD7688

AD7983

ADA4841-x

AD7684 AD7694 AD7693

18-Bit AD7691

AD7690

AD7982

ADA4941-x

AD7984

ADA4841-x

Pin-for-pin compatible.

Summary of content (24 pages)

PAGE 1
8-Bit, 1.33 MSPS PulSAR 10.5 mW ADC in MSOP/QFN AD7984 FEATURES APPLICATION DIAGRAM 18-bit resolution with no missing codes Throughput: 1.33 MSPS Low power dissipation: 10.5 mW at 1.33 MSPS INL: ±2.25 LSB maximum Dynamic range: 99.7 dB typical True differential analog input range: ±VREF 0 V to VREF with VREF between 2.9 V to 5.0 V Allows use of any input range Easy to drive with the ADA4941 No pipeline delay Single-supply 2.5 V operation with 1.8 V/2.
PAGE 2
AD7984 TABLE OF CONTENTS Features .............................................................................................. 1 Driver Amplifier Choice ........................................................... 14 Applications ....................................................................................... 1 Single-to-Differential Driver .................................................... 15 Application Diagram ........................................................................
PAGE 3
AD7984 SPECIFICATIONS VDD = 2.5 V, VIO = 2.3 V to 5.5 V, REF = 5 V, TA = −40°C to +85°C, unless otherwise noted. Table 2.
PAGE 4
AD7984 VDD = 2.5 V, VIO = 2.3 V to 5.5 V, REF = 5 V, TA = −40°C to +85°C, unless otherwise noted. Table 3.
PAGE 5
AD7984 TIMING SPECIFICATIONS TA = −40°C to +85°C, VDD = 2.37 V to 2.63 V, VIO = 2.3 V to 5.5 V, unless otherwise noted. 1 Table 4. Parameter Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions CNV Pulse Width (CS Mode) SCK Period (CS Mode) VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V SCK Period (Chain Mode) VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.
PAGE 6
AD7984 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Analog Inputs IN+, IN− to GND 1 Supply Voltage REF, VIO to GND VDD to GND VDD to VIO Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature θJA Thermal Impedance 10-Lead MSOP 10-Lead QFN (LFCSP) θJC Thermal Impedance 10-Lead MSOP 10-Lead QFN (LFCSP) Lead Temperatures Vapor Phase (60 sec) Infrared (15 sec) 1 Rating −0.3 V to VREF + 0.3 V or ±130 mA −0.3 V to +6.0 V −0.3 V to +3.0 V +3 V to −6 V −0.3 V to VIO + 0.3 V −0.
PAGE 7
AD7984 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD 2 IN+ 3 IN– 4 IN+ 3 10 VIO AD7984 9 SDI TOP VIEW (Not to Scale) 8 SCK 7 SDO 6 CNV GND 5 IN– 4 GND 5 06973-004 REF 1 AD7984 (EXPOSED PAD)* 9 SDI 8 SCK 7 SDO 6 CNV *EXPOSED PADDLE CAN BE CONNECTED TO GROUND. Figure 4. 10-Lead MSOP Pin Configuration 06973-005 10 VIO REF 1 VDD 2 Figure 5. 10-Lead QFN (LFCSP) Pin Configuration Table 6. Pin Function Descriptions Pin No.
PAGE 8
AD7984 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 2.5 V, REF = 5.0 V, VIO = 3.3 V. 2.0 2.0 POSITIVE DNL: +0.63LSB NEGATIVE DNL: –0.34LSB 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 0 65536 131072 –2.0 262144 196608 06973-038 DNL (LSB) 1.5 06973-032 INL (LSB) POSITIVE INL: +1.07LSB NEGATIVE INL: –0.73LSB 0 65536 131072 CODE 262144 196608 CODE Figure 6. Integral Nonlinearity vs. Code Figure 9. Differential Nonlinearity vs.
PAGE 9
AD7984 100 18 –100 17 –105 SNR 95 16 THD (dB) 90 ENOB (Bits) SNR, SINAD (dB) SINAD –110 ENOB 15 3.0 3.5 4.0 4.5 14 5.5 5.0 –120 2.5 06973-043 80 2.5 –115 REFERENCE VOLTAGE (V) 06973-045 85 3.0 3.5 4.0 4.5 5.5 5.0 REFERENCE VOLTAGE (V) Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage Figure 15. THD vs.
PAGE 10
AD7984 2.5 2.5 IVDD 1.5 1.0 IREF 0.5 0 2.375 06973-035 IVIO 2.425 2.475 2.525 2.625 2.575 VDD VOLTAGE (V) 1.4 1.2 IVDD + IVIO 1.1 1.0 0.9 0.8 0.7 06973-036 STANDBY CURRENTS (mA) 1.3 0.6 –15 5 25 45 1.0 IREF 0.5 IVIO 0 –55 –35 –15 5 25 45 65 85 Figure 20. Operating Currents vs. Temperature 1.5 –35 1.5 TEMPERATURE (°C) Figure 18. Operating Currents vs. Supply 0.5 –55 2.0 06973-037 OPERATING CURRENTS (mA) OPERATING CURRENTS (mA) IVDD 2.
PAGE 11
AD7984 TERMINOLOGY Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 22).
PAGE 12
AD7984 THEORY OF OPERATION IN+ SWITCHES CONTROL MSB REF 131,072C 65,536C LSB 4C 2C C SW+ C BUSY COMP GND 131,072C 65,536C 4C 2C C CONTROL LOGIC C MSB OUTPUT CODE LSB SW– 06973-011 CNV IN– Figure 21. ADC Simplified Schematic CIRCUIT INFORMATION The AD7984 is a fast, low power, single-supply, precise, 18-bit ADC using a successive approximation architecture and is capable of converting 1,330,000 samples per second (1.33 MSPS).
PAGE 13
AD7984 Transfer Functions Table 7. Output Codes and Ideal Input Voltages Description FSR − 1 LSB Midscale + 1 LSB Midscale Midscale − 1 LSB −FSR + 1 LSB −FSR 011 ... 111 011 ... 110 011 ... 101 1 2 100 ... 010 Analog Input VREF = 5 V +4.999962 V +38.15 μV 0V −38.15 μV −4.999962 V −5 V Digital Output Code (Hex) 0x1FFFF1 0x00001 0x00000 0x3FFFF 0x20001 0x200002 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND).
PAGE 14
AD7984 ANALOG INPUTS Figure 24 shows an equivalent circuit of the input structure of the AD7984. The two diodes, D1 and D2, provide ESD protection for the analog inputs, IN+ and IN−. Care must be taken to ensure that the analog input signal does not exceed the reference input voltage (REF) by more than 0.3 V. If the analog input signal exceeds this level, the diodes become forward-biased and start conducting current. These diodes can handle a forward-biased current of 130 mA maximum.
PAGE 15
AD7984 SINGLE-TO-DIFFERENTIAL DRIVER If an unbuffered reference voltage is used, the decoupling value depends on the reference used. For instance, a 22 μF (X5R, 1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift ADR43x reference. For applications using a single-ended analog signal, either bipolar or unipolar, the ADA4941-x single-ended-todifferential driver allows for a differential input into the part. The schematic is shown in Figure 26.
PAGE 16
AD7984 DIGITAL INTERFACE Although the AD7984 has a reduced number of pins, it offers flexibility in its serial interface modes. When in CS mode, the AD7984 is compatible with SPI, QSPI, digital hosts, and DSPs. In this mode, the AD7984 can use either a 3-wire or 4-wire interface. A 3-wire interface using the CNV, SCK, and SDO signals minimizes wiring connections useful, for instance, in isolated applications.
PAGE 17
AD7984 high for the maximum possible conversion time to avoid the generation of the busy signal indicator. When the conversion is complete, the AD7984 enters the acquisition phase and goes into standby mode. When CNV goes low, the MSB is output onto SDO. The remaining data bits are clocked by subsequent SCK falling edges. The data is valid on both SCK edges.
PAGE 18
AD7984 CS MODE, 3-WIRE WITH BUSY INDICATOR When the conversion is complete, SDO goes from high impedance to low impedance. With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. The AD7984 then enters the acquisition phase and goes into standby mode. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges.
PAGE 19
AD7984 CS MODE, 4-WIRE WITHOUT BUSY INDICATOR but SDI must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. When the conversion is complete, the AD7984 enters the acquisition phase and goes into standby mode. Each ADC result can be read by bringing its SDI input low, which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges.
PAGE 20
AD7984 used to select other SPI devices, such as analog multiplexers, but SDI must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. When the conversion is complete, SDO goes from high impedance to low impedance. With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host.
PAGE 21
AD7984 readback. When the conversion is complete, the MSB is output onto SDO and the AD7984 enters the acquisition phase and goes into standby mode. The remaining data bits stored in the internal shift register are clocked by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 18 × N clocks are required to read back the N ADCs. The data is valid on both SCK edges.
PAGE 22
AD7984 subsequent data readback. When all ADCs in the chain have completed their conversions, the SDO pin of the ADC closest to the digital host (see the AD7984 ADC labeled C in Figure 38) is driven high. This transition on SDO can be used as a busy indicator to trigger the data readback controlled by the digital host. The AD7984 then enters the acquisition phase and goes into standby mode. The data bits stored in the internal shift register are clocked out, MSB first, by subsequent SCK falling edges.
PAGE 23
AD7984 APPLICATION HINTS LAYOUT The printed circuit board (PCB) that houses the AD7984 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7984, with its analog signals on the left side and its digital signals on the right side, eases this task. AD7984 At least one ground plane should be used. It can be common or split between the digital and analog sections.
PAGE 24
AD7984 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 5.15 4.90 4.65 6 1 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 0.70 0.55 0.40 0.23 0.13 6° 0° 091709-A 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 42. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 2.48 2.38 2.23 3.10 3.00 SQ 2.90 0.50 BSC 6 PIN 1 INDEX AREA 1.74 1.64 1.49 EXPOSED PAD 0.50 0.40 0.30 5 TOP VIEW 0.80 0.75 0.70 0.