Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External MSOP 10

16-Bit, 1.33 MSPS PulSAR ADC in

MSOP/QFN

AD7983

Rev. A

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FEATURES

16-bit resolution with no missing codes

Throughput: 1.33 MSPS

Low power dissipation: 10.5 mW typical @ 1.33 MSPS

INL: ±0.6 LSB typical, ±1.0 LSB maximum

SINAD: 91.6 dB @ 10 kHz

THD: −115 dB @ 10 kHz

Pseudo differential analog input range

0 V to V

REF

with V

REF

between 2.9 V to 5.5 V

Any input range and easy to drive with the ADA4841

No pipeline delay

Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V logic

interface

Serial interface SPI-/QSPI™-/MICROWIRE™-/DSP-compatible

Daisy-chain multiple ADCs and busy indicator

10-lead MSOP (MSOP-8 size) and 10-lead 3 mm × 3 mm QFN

(LFCSP), SOT-23 size

Wide operating temperature range: −40°C to +85°C

APPLICATIONS

Battery-powered equipment

Communications

ATE

Data acquisitions

Medical instruments

APPLICATION DIAGRAM

AD7983

REF

GND

VDD

IN+

IN–

VIO

SDI

SCK

SDO

CNV

1.8V TO 5V

3- OR 4-WIRE INTERFACE

(SPI, DAISY CHAIN, CS)

2.9

TO 5V 2.5

TO VREF

06974-001

Figure 1.

GENERAL DESCRIPTION

The AD7983 is a 16-bit, successive approximation, analog-to-

digital converter (ADC) that operates from a single power

supply, VDD. It contains a low power, high speed, 16-bit

sampling ADC and a versatile serial interface port. On the CNV

rising edge, it samples an analog input IN+ between 0 V to REF

with respect to a ground sense IN−. The reference voltage, REF,

is applied externally and can be set independent of the supply

voltage, VDD. Its power scales linearly with throughput.

The SPI-compatible serial interface also features the ability,

using the SDI input, to daisy-chain several ADCs on a single,

3-wire bus and provides an optional busy indicator. It is

compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate

supply VIO.

The AD7983 is housed in a 10-lead MSOP or a 10-lead QFN

(LFCSP) with operation specified from −40°C to +85°C.

Table 1. MSOP, QFN (LFCSP) 14-/16-/18-Bit PulSAR® ADC

Type 100 kSPS 250 kSPS 400 kSPS to 500 kSPS ≥1000 kSPS ADC Driver

14-Bit AD7940 AD7942

AD7946

16-Bit AD7680

AD7685

AD7686

AD7980

ADA4941

AD7683 AD7687

AD7688

AD7983

ADA4841

AD7684 AD7694 AD7693

18-Bit AD7691

AD7690

AD7982

ADA4941

AD7984

ADA4841

Pin-for-pin compatible.

Summary of content (24 pages)

PAGE 1
6-Bit, 1.33 MSPS PulSAR ADC in MSOP/QFN AD7983 APPLICATION DIAGRAM 2.9V TO 5V 16-bit resolution with no missing codes Throughput: 1.33 MSPS Low power dissipation: 10.5 mW typical @ 1.33 MSPS INL: ±0.6 LSB typical, ±1.0 LSB maximum SINAD: 91.6 dB @ 10 kHz THD: −115 dB @ 10 kHz Pseudo differential analog input range 0 V to VREF with VREF between 2.9 V to 5.5 V Any input range and easy to drive with the ADA4841 No pipeline delay Single-supply 2.5 V operation with 1.8 V/2.
PAGE 2
AD7983 TABLE OF CONTENTS Features .............................................................................................. 1 Driver Amplifier Choice ........................................................... 14 Applications ....................................................................................... 1 Voltage Reference Input ............................................................ 15 Application Diagram ........................................................................
PAGE 3
AD7983 SPECIFICATIONS VDD = 2.5 V, VIO = 2.3 V to 5.5 V, REF = 5 V, TA = –40°C to +85°C, unless otherwise noted. Table 2.
PAGE 4
AD7983 VDD = 2.5 V, VIO = 2.3 V to 5.5 V, REF = 5 V, TA = –40°C to +85°C, unless otherwise noted. Table 3.
PAGE 5
AD7983 TIMING SPECIFICATIONS TA = −40°C to +85°C, VDD = 2.37 V to 2.63 V, VIO = 3.3 V to 5.5 V, unless otherwise noted. See Figure 2 and Figure 3 for load conditions. Table 4. Parameter Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions CNV Pulse Width (CS Mode) SCK Period (CS Mode) VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V SCK Period (Chain Mode) VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.
PAGE 6
AD7983 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Analog Inputs IN+, 1 IN−1 to GND Supply Voltage REF, VIO to GND VDD to GND VDD to VIO Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature θJA Thermal Impedance 10-Lead MSOP 10-Lead QFN (LFCSP) θJC Thermal Impedance 10-Lead MSOP 10-Lead QFN (LFCSP) Lead Temperature Vapor Phase (60 sec) Infrared (15 sec) 1 Rating −0.3 V to VREF + 0.3 V or ±130 mA −0.3 V to +6 V −0.3 V to +3 V +3 V to −6 V −0.3 V to VIO + 0.3 V −0.
PAGE 7
AD7983 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 9 SDI 8 SCK 7 SDO 6 CNV IN+ 3 IN– 4 AD7983 TOP VIEW (Not to Scale) GND 5 REF 1 10 VIO VDD 2 9 SDI IN+ 3 IN– 4 GND 5 AD7983 TOP VIEW (Not to Scale) 8 SCK 7 SDO 6 CNV 06974-005 10 VIO 06974-004 REF 1 VDD 2 Figure 5. 10-Lead QFN (LFCSP) Pin Configuration Figure 4. 10-Lead MSOP Pin Configuration Table 6. Pin Function Descriptions Pin No.
PAGE 8
AD7983 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 2.5 V, REF = 5 V, VIO = 3.3 V, unless otherwise noted. 1.25 1.00 POSITIVE INL: 0.30LSB NEGATIVE INL: –0.37LSB 1.00 POSITIVE DNL: 0.14LSB NEGATIVE DNL: –0.14LSB 0.75 0.75 0.50 0.25 DNL (LSB) INL (LSB) 0.50 0 –0.25 0.25 0 –0.25 –0.50 –0.50 –0.75 0 16384 32768 –1.00 65536 49152 06974-029 –1.25 –0.75 06974-026 –1.00 0 16384 32768 CODE 65536 49152 CODE Figure 6. Integral Nonlinearity vs. Code Figure 9. Differential Nonlinearity vs.
PAGE 9
–110 95 –112 93 –114 91 SNR (dB) –116 89 06974-038 –35 –15 5 25 45 65 85 105 85 –55 125 –35 –15 5 25 45 65 85 105 Figure 12. THD vs. Temperature Figure 15. SNR vs. Temperature –105 130 –110 125 16 100 15 SNR ENOB SNR, SINAD (dB) 115 SFDR (dB) 120 THD –120 90 SFDR SINAD 85 14 13 110 –130 2.5 3.0 3.5 4.0 4.5 5.0 105 5.5 REFERENCE VOLTAGE (V) 80 2.5 06974-033 –125 3.0 3.5 4.0 4.5 5.0 12 5.5 REFERENCE VOLTAGE (V) Figure 13. THD, SFDR vs.
PAGE 10
AD7983 1.5 2.5 1.4 1.3 2.0 STANDBY CURRENTS (mA) 1.5 1.0 IREF 0 2.375 06974-036 IVIO 2.425 2.475 2.525 2.575 2.625 1.0 0.9 0.8 2.5 IVDD 2.0 1.5 1.0 IREF –15 5 25 06974-039 IVIO –35 45 0.5 –55 –35 –15 5 25 45 65 85 Figure 20. Standby Currents vs. Temperature Figure 18. Operating Currents vs. Supply 0.5 0.6 TEMPERATURE (°C) VDD VOLTAGE (V) OPERATING CURRENTS (mA) IVDD + IVIO 1.1 0.7 0.5 0 –55 1.
PAGE 11
AD7983 TERMINOLOGY Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 22).
PAGE 12
AD7983 THEORY OF OPERATION IN+ MSB LSB 32,768C 16,384C 4C 2C C SWITCHES CONTROL SW+ C BUSY REF COMP GND 32,768C 16,384C 4C 2C C CONTROL LOGIC OUTPUT CODE C LSB SW+ CNV 06974-006 MSB IN– Figure 21. ADC Simplified Schematic CIRCUIT INFORMATION The AD7983 is a fast, low power, single-supply, precise 16-bit ADC that uses a successive approximation architecture. The AD7983 is capable of converting 1,000,000 samples per second (1 MSPS) and powers down between conversions.
PAGE 13
AD7983 Transfer Functions Table 7. Output Codes and Ideal Input Voltages The ideal transfer characteristic for the AD7983 is shown in Figure 22 and Table 7. Description FSR − 1 LSB Midscale + 1 LSB Midscale Midscale − 1 LSB −FSR + 1 LSB −FSR 111 ... 101 1 2 Analog Input Digital Output Code (Hex) FFFF1 8001 8000 7FFF 0001 00002 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND). This is also the code for an underranged analog input (VIN+ − VIN− below VGND).
PAGE 14
AD7983 ANALOG INPUTS DRIVER AMPLIFIER CHOICE Figure 24 shows an equivalent circuit of the input structure of the AD7983. Although the AD7983 is easy to drive, the driver amplifier needs to meet the following requirements: The two diodes, D1 and D2, provide ESD protection for the analog inputs, IN+ and IN−. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 V, because this causes these diodes to become forwardbiased and start conducting current.
PAGE 15
AD7983 VOLTAGE REFERENCE INPUT POWER SUPPLY The AD7983 voltage reference input, REF, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the REF and GND pins, as explained in the Layout section. The AD7983 uses two power supply pins: a core supply (VDD) and a digital input/output interface supply (VIO). VIO allows direct interface with any logic between 1.8 V and 5.0 V.
PAGE 16
AD7983 DIGITAL INTERFACE Though the AD7983 has a reduced number of pins, it offers flexibility in its serial interface modes. When in CS mode, the AD7983 is compatible with SPI, QSPI, and digital hosts. This interface can use either a 3-wire or a 4-wire interface. A 3-wire interface using the CNV, SCK, and SDO signals minimizes wiring connections useful, for instance, in isolated applications.
PAGE 17
AD7983 When CNV goes low, the MSB is output onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate provided that it has an acceptable hold time. After the 16th SCK falling edge or when CNV goes high, whichever is earlier, SDO returns to high impedance.
PAGE 18
AD7983 If multiple AD7983s are selected at the same time, the SDO output pin handles this contention without damage or induced latch-up. Meanwhile, it is recommended that this contention be kept as short as possible to limit extra power dissipation. CS MODE, 3-WIRE WITH BUSY INDICATOR This mode is usually used when a single AD7983 is connected to an SPI-compatible digital host that has an interrupt input. The connection diagram is shown in Figure 28, and the corresponding timing is given in Figure 29.
PAGE 19
AD7983 When the conversion is complete, the AD7983 enters the acquisition phase and goes into standby mode. Each ADC result can be read by bringing its SDI input low, which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate provided it has an acceptable hold time.
PAGE 20
AD7983 With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. The AD7983 then enters the acquisition phase and goes into standby mode. The data bits are clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate provided it has an acceptable hold time.
PAGE 21
AD7983 When SDI and CNV are low, SDO is driven low. With SCK low, a rising edge on CNV initiates a conversion, selects the chain mode, and disables the busy indicator. In this mode, CNV is held high during the conversion phase and the subsequent data readback. When the conversion is complete, the MSB is output onto SDO and the AD7983 enters the acquisition phase and goes into standby mode. The remaining data bits stored in the internal shift register are clocked by subsequent SCK falling edges.
PAGE 22
AD7983 When SDI and CNV are low, SDO is driven low. With SCK high, a rising edge on CNV initiates a conversion, selects the chain mode, and enables the busy indicator feature. In this mode, CNV is held high during the conversion phase and the subsequent data readback. When all ADCs in the chain have completed their conversions, the SDO pin of the ADC closest to the digital host (see the AD7983 ADC labeled C in Figure 36) is driven high.
PAGE 23
AD7983 APPLICATION HINTS LAYOUT The printed circuit board (PCB) that houses the AD7983 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7983, with all its analog signals on the left side and all its digital signals on the right side, eases this task. AD7983 At least one ground plane should be used. It can be common or split between the digital and analog section.
PAGE 24
AD7983 OUTLINE DIMENSIONS 3.10 3.00 2.90 6 10 3.10 3.00 2.90 1 5 5.15 4.90 4.65 PIN 1 0.50 BSC 0.95 0.85 0.75 1.10 MAX 0.15 0.05 0.33 0.17 SEATING PLANE 0.80 0.60 0.40 8° 0° 0.23 0.08 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 40.10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 0.30 0.23 0.18 0.50 BSC 10 6 PIN 1 INDEX AREA *EXPOSED PAD (BOTTOM VIEW) 0.50 0.40 0.30 5 TOP VIEW 0.80 MAX 0.55 NOM 0.80 0.75 0.70 SEATING PLANE 1 2.