Datasheet

Data Sheet AD7982
Rev. B | Page 19 of 24
CS
MODE, 4-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when multiple AD7982s are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7982s is shown in
Figure 33, and the corresponding timing is given in Figure 34.
With SDI high, a rising edge on CNV initiates a conversion,
selects the
CS
mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
time elapses and then held high for the maximum possible
conversion time to avoid the generation of the busy signal
indicator. When the conversion is complete, the AD7982 enters
the acquisition phase and powers down. Each ADC result can
be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are then
clocked by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can be used to
capture the data, a digital host using the SCK falling edge allows
a faster reading rate, provided it has an acceptable hold time.
After the 18
th
SCK falling edge or when SDI goes high (whichever
occurs first), SDO returns to high impedance and another
AD7982 can be read.
AD7982
SDI
SDO
CNV
SCK
CONVERT
DATA IN
CLK
DIGITAL HOST
06513-020
CS1
CS2
AD7982
SDI
SDO
CNV
SCK
Figure 33.
CS
Mode, 4-Wire Without Busy Indicator Connection Diagram
SDO
D17 D16 D15 D1 D0
t
DIS
SCK
1 2 3 34 35 36
t
HSDO
t
DSDO
t
EN
CONVERSIONACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
SDI(CS1)
CNV
t
SSDICNV
t
HSDICNV
D1
16 17
t
SCK
t
SCKL
t
SCKH
D0 D17 D16
19 2018
SDI(CS2)
06513-021
Figure 34.
CS
Mode, 4-Wire Without Busy Indicator Serial Interface Timing