Datasheet

Data Sheet AD7982
Rev. B | Page 15 of 24
SINGLE-TO-DIFFERENTIAL DRIVER
For applications using a single-ended analog signal, either
bipolar or unipolar, the ADA4941 single-ended-to-differential
driver allows for a differential input to the part. The schematic
is shown in Figure 26.
R1 and R2 set the attenuation ratio between the input range and
the ADC range (V
REF
). R1, R2, and C
F
are chosen depending on
the desired input resistance, signal bandwidth, antialiasing, and
noise contribution. For example, for the ±10 V range with a 4 kΩ
impedance, R2 = 1 kΩ and R1 = 4 kΩ.
R3 and R4 set the common mode on the IN− input, and R5 and R6
set the common mode on the IN+ input of the ADC. The common
mode should be close to V
REF
/2. For example, for the ±10 V range
with a single supply, R3 = 8.45 kΩ, R4 = 11.8 kΩ, R5 = 10.5 kΩ,
and R6 = 9.76 kΩ.
06513-015
20Ω
20Ω
10µF
R1
100nF
+2.5V
+5V REF
+5.2V
–0.2V
C
F
R2
R4
R6
±10V,
±5V, ..
R3
R5
REF
VDD
GND
IN+
IN–
AD7982
2.7nF
2.7nF
ADA4941
IN
FB
OUTP
OUTN
REF
100nF
Figure 26. Single-Ended-to-Differential Driver Circuit
VOLTAGE REFERENCE INPUT
The AD7982 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
When REF is driven by a very low impedance source (for
example, a reference buffer using the AD8031 or the AD8605),
a 10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate
for optimum performance.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 μF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR43x reference.
If desired, a reference decoupling capacitor with values as small
as 2.2 μF can be used with a minimal impact on performance,
especially DNL.
Regardless, there is no need for an additional lower value ceramic
decoupling capacitor (for example, 100 nF) between the REF
and GND pins.
POWER SUPPLY
The AD7982 uses two power supply pins: a core supply (VDD) and
a digital input/output interface supply (VIO). VIO allows direct
interface with any logic between 1.8 V and 5.5 V. To reduce the
number of supplies needed, VIO and VDD can be tied together.
The AD7982 is independent of power supply sequencing between
VIO and VDD. Additionally, it is very insensitive to power supply
variations over a wide frequency range, as shown in Figure 27.
95
90
85
80
75
70
65
60
PSRR (dB)
1 10 100 1000
FREQUENCY (kHz)
06513-039
Figure 27. PSRR vs. Frequency
To ensure optimum performance, VDD should be roughly half
of REF, the voltage reference input. For example, if REF is 5.0 V,
VDD should be set to 2.5 V (±5%).
The AD7982 powers down automatically at the end of each
conversion phase; therefore, the power scales linearly with the
sampling rate. This makes the part ideal for low sampling rates
(even of a few hertz) and low battery-powered applications.
06513-037
10.000
1.000
0.100
0.010
0.001
OPER
A
TING CURRENTS (mA)
100000
SAMPLING RATE (SPS)
10000 1000000
I
VDD
I
VIO
I
REF
Figure 28. Operating Currents vs. Sampling Rate