Datasheet

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16-Bit, 1 MSPS PulSAR ADC in MSOP/QFN

Data Sheet

AD7980

Rev. C Document Feedback

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FEATURES

16-bit resolution with no missing codes

Throughput: 1 MSPS

Low power dissipation

4 mW at 1 MSPS (VDD only)

7 mW at 1 MSPS (total)

70 µW at 10 kSPS

INL: ±0.6 LSB typical, ±1.25 LSB maximum

SINAD: 91.25 dB at 10 kHz

THD: −110 dB at 10 kHz

Pseudo differential analog input range

0 V to V

REF

with V

REF

between 2.5 V to 5.5 V

Any input range and easy to drive with the ADA4841

No pipeline delay

Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V

logic interface

Serial interface SPI-/QSPI™-/MICROWIRE™-/DSP-compatible

Daisy-chain multiple ADCs and busy indicator

10-lead MSOP and 10-lead, 3 mm × 3 mm, QFN (LFCSP),

same space as SOT-23

Wide operating temperature range: −40°C to +125°C

APPLICATIONS

Battery-powered equipment

Communications

ATE

Data acquisitions

Medical instruments

APPLICATION DIAGRAM EXAMPLE

AD7980

REF

GND

VDD

IN+

IN–

VIO

SDI

SCK

SDO

CNV

1.8V TO 5V

3- OR 4-WIRE INTERFACE

(SPI, DAISY CHAIN, CS)

2.5V TO 5V 2.5V

0 TO VREF

06392-001

Figure 1.

GENERAL DESCRIPTION

The AD7980 is a 16-bit, successive approximation, analog-to-

digital converter (ADC) that operates from a single power

supply, VDD. It contains a low power, high speed, 16-bit

sampling ADC and a versatile serial interface port. On the CNV

rising edge, it samples an analog input IN+ between 0 V to REF

with respect to a ground sense IN−. The reference voltage, REF,

is applied externally and can be set independent of the supply

voltage, VDD. Its power scales linearly with throughput.

The SPI-compatible serial interface also features the ability,

using the SDI input, to daisy-chain several ADCs on a single,

3-wire bus and provides an optional busy indicator. It is compatible

with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate supply VIO.

The AD7980 is housed in a 10-lead MSOP or a 10-lead QFN

(LFCSP) with operation specified from −40°C to +125°C.

Table 1. MSOP, QFN (LFCSP) 14-/16-/18-Bit PulSAR® ADC

Type 100 kSPS 250 kSPS 400 kSPS to 500 kSPS 1000 kSPS ADC Driver

18-Bit AD7691

AD7690

AD7982

ADA4941

ADA4841

16-Bit AD7680 AD7685

AD7686

AD7980

ADA4941

AD7683 AD7687

AD7688

ADA4841

AD7684

AD7694

AD7693

14-Bit AD7940 AD7942

AD7946

Pin-for-pin compatible.

Summary of content (28 pages)

PAGE 1
6-Bit, 1 MSPS PulSAR ADC in MSOP/QFN AD7980 Data Sheet FEATURES APPLICATION DIAGRAM EXAMPLE 2.5V TO 5V 16-bit resolution with no missing codes Throughput: 1 MSPS Low power dissipation 4 mW at 1 MSPS (VDD only) 7 mW at 1 MSPS (total) 70 µW at 10 kSPS INL: ±0.6 LSB typical, ±1.25 LSB maximum SINAD: 91.25 dB at 10 kHz THD: −110 dB at 10 kHz Pseudo differential analog input range 0 V to VREF with VREF between 2.5 V to 5.
PAGE 2
AD7980 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Driver Amplifier Choice ........................................................... 15 Applications ....................................................................................... 1 Voltage Reference Input ............................................................ 16 Application Diagram Example........................................................
PAGE 3
Data Sheet AD7980 SPECIFICATIONS VDD = 2.5 V, VIO = 2.3 V to 5.5 V, VREF = 5 V, TA = –40°C to +125°C, unless otherwise noted. Table 2.
PAGE 4
AD7980 Data Sheet VDD = 2.5 V, VIO = 2.3 V to 5.5 V, VREF = 5 V, TA = –40°C to +125°C, unless otherwise noted. Table 3.
PAGE 5
Data Sheet AD7980 TIMING SPECIFICATIONS −40°C to +125°C, VDD = 2.37 V to 2.63 V, VIO = 3.3 V to 5.5 V, unless otherwise stated. See Figure 2 and Figure 3 for load conditions. Table 4. Parameter Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions CNV Pulse Width (CS Mode) SCK Period (CS Mode) VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V SCK Period (Chain Mode) VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.
PAGE 6
AD7980 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Analog Inputs IN+, 1 IN−1 to GND Supply Voltage REF, VIO to GND VDD to GND VDD to VIO Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature θJA Thermal Impedance (10-Lead MSOP) θJC Thermal Impedance (10-Lead MSOP) Lead Temperature Vapor Phase (60 sec) Infrared (15 sec) 1 Rating −0.3 V to VREF + 0.3 V or ±130 mA −0.3 V to +6 V −0.3 V to +3 V +3 V to −6 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.
PAGE 7
Data Sheet AD7980 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS REF 1 VDD 2 IN+ 3 REF 1 10 VIO VDD 2 9 AD7980 SDI 8 SCK TOP VIEW (Not to Scale) 7 SDO IN– 4 10 VIO AD7980 TOP VIEW (Not to Scale) 9 SDI 8 SCK IN– 4 7 SDO GND 5 6 CNV 6 CNV 06392-004 GND 5 NOTES 1. CONNECT THE EXPOSED PAD TO GND. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES. Figure 4. 10-Lead MSOP Pin Configuration 06392-005 IN+ 3 Figure 5. 10-Lead QFN (LFCSP) Pin Configuration Table 6.
PAGE 8
AD7980 Data Sheet TERMINOLOGY Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 26).
PAGE 9
Data Sheet AD7980 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 2.5 V, VREF = 5.0 V, VIO = 3.3 V, unless otherwise noted. 1.25 1.00 POSITIVE INL: +0.33 LSB NEGATIVE INL: –0.39 LSB 1.00 POSITIVE INL: +0.18 LSB NEGATIVE INL: –0.21 LSB 0.75 0.75 0.50 0.25 DNL (LSB) INL (LSB) 0.50 0 –0.25 0.25 0 –0.25 –0.50 –0.50 –0.75 –1.25 49152 32768 16384 0 06392-039 –0.75 06392-036 –1.00 –1.00 65536 0 16384 32768 CODE Figure 6. Integral Nonlinearity vs. Code, REF = 5 V 1.25 65536 Figure 9.
PAGE 10
AD7980 Data Sheet 180k 60k 168591 52212 160k 50k 140k 40k COUNTS 100k 80k 60k 32417 20k 52710 38751 40k 06392-042 10k 20k 0 31340 30k 0 27 0 1201 829 33 2 0 0 0 7225 0 0 8003 8004 8005 8006 8007 8008 8009 800A 800B 800C 800D 800E 800F 0 6807 539 16 502 14 0 06392-059 COUNTS 120k 0 7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8006 CODE IN HEX CODE IN HEX Figure 15. Histogram of a DC Input at the Code Center, REF = 2.5 V Figure 12.
PAGE 11
Data Sheet AD7980 100 –85 –90 –95 –100 THD (dB) 90 –105 –110 –115 85 06392-063 –120 80 10 100 06392-064 SINAD (dB) 95 –125 10 1000 100 FREQUENCY (kHz) Figure 21. THD vs. Frequency 95 –110 93 –112 91 –114 THD (dB) 89 87 –116 06392-049 –118 –35 –15 5 45 25 65 85 105 –120 –55 125 06392-052 SNR (dB) Figure 18. SINAD vs. Frequency 85 –55 –35 –15 TEMPERATURE (°C) 85 105 125 85 105 125 1.4 1.4 IVDD IVDD 1.2 1.0 1.0 CURRENT (mA) 1.2 0.8 0.6 IREF 0.8 0.
PAGE 12
AD7980 Data Sheet 8 7 5 4 3 IVDD + IVIO 2 1 0 –55 06392-054 CURRENT (µA) 6 –35 –15 45 65 5 25 TEMPERATURE (°C) 85 105 125 Figure 24. Power-Down Currents vs. Temperature Rev.
PAGE 13
Data Sheet AD7980 THEORY OF OPERATION IN+ MSB LSB 32,768C 16,384C 4C 2C C SWITCHES CONTROL SW+ C BUSY REF COMP GND 32,768C 16,384C 4C 2C C CONTROL LOGIC OUTPUT CODE C LSB MSB SW+ 06392-011 CNV IN– Figure 25. ADC Simplified Schematic CIRCUIT INFORMATION The AD7980 is a fast, low power, single-supply, precise 16-bit ADC that uses a successive approximation architecture. The AD7980 is capable of converting 1,000,000 samples per second (1 MSPS) and powers down between conversions.
PAGE 14
AD7980 Data Sheet Transfer Functions Table 7. Output Codes and Ideal Input Voltages The ideal transfer characteristic for the AD7980 is shown in Figure 26 and Table 7. Description FSR – 1 LSB Midscale + 1 LSB Midscale Midscale – 1 LSB –FSR + 1 LSB –FSR 111 ... 101 1 2 Analog Input Digital Output Code (Hexa) FFFF1 8001 8000 7FFF 0001 00002 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND).
PAGE 15
Data Sheet AD7980 ANALOG INPUT DRIVER AMPLIFIER CHOICE Figure 28 shows an equivalent circuit of the input structure of the AD7980. Although the AD7980 is easy to drive, the driver amplifier needs to meet the following requirements: The two diodes, D1 and D2, provide ESD protection for the analog inputs, IN+ and IN−. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.
PAGE 16
AD7980 Data Sheet VOLTAGE REFERENCE INPUT When REF is driven by a very low impedance source, for example, a reference buffer using the AD8031 or the AD8605, a ceramic chip capacitor is appropriate for optimum performance. If an unbuffered reference voltage is used, the decoupling value depends on the reference used. For instance, a 22 µF (X5R, 1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift ADR43x reference.
PAGE 17
Data Sheet AD7980 When CNV goes low, the MSB is output onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate provided that it has an acceptable hold time. After the 16th SCK falling edge or when CNV goes high, whichever is earlier, SDO returns to high impedance.
PAGE 18
AD7980 Data Sheet If multiple AD7980s are selected at the same time, the SDO output pin handles this contention without damage or induced latch-up. Meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation. CS MODE 3-WIRE WITH BUSY INDICATOR This mode is usually used when a single AD7980 is connected to an SPI-compatible digital host having an interrupt input. The connection diagram is shown in Figure 33, and the corresponding timing is given in Figure 34.
PAGE 19
Data Sheet AD7980 When the conversion is complete, the AD7980 enters the acquisition phase and powers down. Each ADC result can be read by bringing its SDI input low, which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate provided it has an acceptable hold time.
PAGE 20
AD7980 Data Sheet With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. The AD7980 then enters the acquisition phase and powers down. The data bits are clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate provided it has an acceptable hold time.
PAGE 21
Data Sheet AD7980 CHAIN MODE, WITHOUT BUSY INDICATOR When SDI and CNV are low, SDO is driven low. With SCK low, a rising edge on CNV initiates a conversion, selects the chain mode, and disables the Busy indicator. In this mode, CNV is held high during the conversion phase and the subsequent data readback. When the conversion is complete, the MSB is output onto SDO and the AD7980 enters the acquisition phase and powers down.
PAGE 22
AD7980 Data Sheet CHAIN MODE WITH BUSY INDICATOR When SDI and CNV are low, SDO is driven low. With SCK high, a rising edge on CNV initiates a conversion, selects the chain mode, and enables the busy indicator feature. In this mode, CNV is held high during the conversion phase and the subsequent data readback. When all ADCs in the chain have completed their conversions, the SDO pin of the ADC closest to the digital host (see the AD7980 ADC labeled C in Figure 41) is driven high.
PAGE 23
Data Sheet AD7980 APPLICATION HINTS LAYOUT The printed circuit board (PCB) that houses the AD7980 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7980, with all its analog signals on the left side and all its digital signals on the right side, eases this task. AD7980 At least one ground plane should be used. It can be common or split between the digital and analog section.
PAGE 24
AD7980 Data Sheet OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 0.70 0.55 0.40 0.23 0.13 6° 0° 091709-A 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 45.10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 2.48 2.38 2.23 3.10 3.00 SQ 2.90 0.50 BSC 10 6 1.74 1.64 1.49 EXPOSED PAD 0.50 0.40 0.30 0.80 0.75 0.70 SEATING PLANE 0.30 0.
PAGE 25
Data Sheet AD7980 ORDERING GUIDE Model 1, 2, 3 AD7980ARMZ AD7980ARMZRL7 AD7980BRMZ AD7980BRMZRL7 AD7980ACPZ-RL AD7980ACPZ-RL7 AD7980BCPZ-RL AD7980BCPZ-RL7 AD7980BCPZ-R2 EVAL-AD7980SDZ EVAL-SDP-CB1Z 1 2 3 Integral Nonlinearity ±2.5 LSB max ±2.5 LSB max ±1.25 LSB max ±1.25 LSB max ±2.5 LSB max ±2.5 LSB max ±1.25 LSB max ±1.25 LSB max ±1.
PAGE 26
AD7980 Data Sheet NOTES Rev.
PAGE 27
Data Sheet AD7980 NOTES Rev.