Datasheet
AD797 Data Sheet
Rev. I | Page 14 of 20
The I-to-V converter is a special case of the follower configu-
ration. When the AD797 is used in an I-to-V converter, for
example as a DAC buffer, the circuit shown in Figure 40 should
be used. The value of C
L
depends on the DAC, and if C
L
is greater
than 33 pF, a 100 Ω series resistor is required. A bypassed balancing
resistor (R
S
and C
S
) can be included to minimize dc errors.
7
*
*
V
OUT
+V
S
–V
S
AD797
00846-039
R
1
R
S
I
IN
C
S
6
3
4
100Ω
600Ω
20pF TO 120pF
2
*USE THE POWER SUPPLY BYPASSING SHOWN IN FIGURE 35.
Figure 40. I-to-V Converter Connection
THE INVERTING CONFIGURATION
The inverting configuration (see Figure 41) presents a low input
impedance, R1, to the source. For this reason, the goals of both
low noise and input buffering are at odds with one another.
Nonetheless, the excellent dynamics of the AD797 makes
it the preferred choice in many inverting applications, and
with careful selection of feedback resistors, the noise penalties
are minimal. Some examples are presented in Table 7 and
Figure 41.
7
*
*
V
OUT
V
IN
+V
S
–V
S
AD797
00846-040
R
2
R
L
R
S
R1
C
L
6
3
4
2
*USE THE POWER SUPP
LY BYP
ASSING SHOWN IN FIGURE 35.
Figure 41. Inverting Amplifier Connection
Table 7. Values for Inverting Circuit
Gain R1 R2 C
L
Noise
(Excluding R
S
)
−1 1 kΩ 1 kΩ ≈ 20 pF 3.0 nV/√Hz
−1 300 Ω 300 Ω ≈ 10 pF 1.8 nV/√Hz
−10 150 Ω 1500 Ω ≈ 5 pF 1.8 nV/√Hz
DRIVING CAPACITIVE LOADS
The capacitive load driving capabilities of the AD797 are
displayed in Figure 42. At gains greater than 10, usually no
special precautions are necessary. If more drive is desirable,
however, the circuit shown in Figure 43 should be used. For
example, this circuit allows a 5000 pF load to be driven cleanly
at a noise gain ≥2.
00846-041
100nF
10nF
1pF
10010
1
1k
1nF
100pF
10pF
CLOSED-LOOP GAIN
CAPACITIVE LOAD DRIVE CAPABILITY
Figure 42. Capacitive Load Drive Capability vs. Closed-Loop Gain
7
*
*
V
OUT
V
IN
+V
S
–V
S
AD797
00846-042
C1
20pF
200pF
6
3
4
2
33Ω
100Ω
1kΩ
1kΩ
*USE THE POWER SUPP
LY
BYPASSING SHOWN IN FIGURE 35.
Figure 43. Recommended Circuit for Driving a High Capacitance Load
SETTLING TIME
The AD797 is unique among ultralow noise amplifiers in that it
settles to 16 bits (<150 μV) in less than 800 ns. Measuring this
performance presents a challenge. A special test circuit (see
Figure 44) was developed for this purpose. The input signal was
obtained from a resonant reed switch pulse generator, available
from Tektronix as calibration Fixture No. 067-0608-00. When
open, the switch is simply 50 Ω to ground and settling is purely
a passive pulse decay and inherently flat. The low repetition rate
signal was captured on a digital oscilloscope after being
amplified and clamped twice. The selection of plug-in for the
oscilloscope was made for minimum overload recovery.