Datasheet

Data Sheet AD7949
Rev. D | Page 7 of 32
VDD = 2.3 V to 4.5 V, VIO = 1.8 V to VDD, all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 4.
Parameter
1
Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available t
CONV
3.2 µs
Acquisition Time t
ACQ
1.8 µs
Time Between Conversions t
CYC
5 µs
Data Write/Read During Conversion
t
DATA
1.2
µs
CNV Pulse Width t
CNVH
10 ns
SCK Period t
SCK
t
DSDO
+ 2 ns
SCK Low Time t
SCKL
12 ns
SCK High Time t
SCKH
12 ns
SCK Falling Edge to Data Remains Valid
t
HSDO
5
ns
SCK Falling Edge to Data Valid Delay t
DSDO
VIO Above 3 V 24 ns
VIO Above 2.7 V 30 ns
VIO Above 2.3 V 38 ns
VIO Above 1.8 V 48 ns
CNV Low to SDO D15 MSB Valid t
EN
VIO Above 3 V 21 ns
VIO Above 2.7 V 27 ns
VIO Above 2.3 V 35 ns
VIO Above 1.8 V 45 ns
CNV High or Last SCK Falling Edge to SDO High Impedance t
DIS
50 ns
CNV Low to SCK Rising Edge t
CLSCK
10 ns
DIN Valid Setup Time from SCK Rising Edge t
SDIN
5 ns
DIN Valid Hold Time from SCK Rising Edge t
HDIN
5 ns
1
See Figure 2 and Figure 3 for load conditions.
I
OL
500µA
500µA
I
OH
1.4V
TO SDO
C
L
50pF
07351-002
Figure 2. Load Circuit for Digital Interface Timing
30% VIO
70% VIO
2V OR VIO – 0.5V
1
0.8V OR 0.5V
2
0.8V OR 0.5V
2
2V OR VIO – 0.5V
1
t
DELAY
t
DELAY
1
2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
2
0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
07351-003
Figure 3. Voltage Levels for Timing