Datasheet

AD7949 Data Sheet
Rev. D | Page 6 of 32
TIMING SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 1.8 V to VDD, all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter
1
Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available t
CONV
2.2 µs
Acquisition Time t
ACQ
1.8 µs
Time Between Conversions t
CYC
4.0 µs
Data Write/Read During Conversion t
DATA
1.0 µs
CNV Pulse Width t
CNVH
10 ns
SCK Period t
SCK
t
DSDO
+ 2 ns
SCK Low Time t
SCKL
11 ns
SCK High Time t
SCKH
11 ns
SCK Falling Edge to Data Remains Valid t
HSDO
4 ns
SCK Falling Edge to Data Valid Delay t
DSDO
VIO Above 2.7 V 18 ns
VIO Above 2.3 V 23 ns
VIO Above 1.8 V 28 ns
CNV Low to SDO D15 MSB Valid t
EN
VIO Above 2.7 V 18 ns
VIO Above 2.3 V
22
ns
VIO Above 1.8 V 25 ns
CNV High or Last SCK Falling Edge to SDO High Impedance t
DIS
32 ns
CNV Low to SCK Rising Edge t
CLSCK
10 ns
DIN Valid Setup Time from SCK Rising Edge t
SDIN
5 ns
DIN Valid Hold Time from SCK Rising Edge t
HDIN
5 ns
1
See Figure 2 and Figure 3 for load conditions.