Datasheet

AD7949 Data Sheet
Rev. D | Page 28 of 32
READ/WRITE SPANNING CONVERSION WITHOUT
A BUSY INDICATOR
This mode is used when the AD7949 is connected to any host
using an SPI, serial port, or FPGA. The connection diagram is
shown in Figure 39, and the corresponding timing is given in
Figure 40. For the SPI, the host should use CPHA = CPOL = 0.
Reading/writing spanning conversion is shown, which covers
all three modes detailed in the Digital Interface section. For this
mode, the host must generate the data transfer based on the
conversion time. For an interrupt driven transfer that uses a
busy indicator, refer to the Read/Write Spanning Conversion
with a Busy Indicator section.
A rising edge on CNV initiates a conversion, forces SDO to
high impedance, and ignores data present on DIN. After a
conversion is initiated, it continues until completion irrespec-
tive of the state of CNV. CNV must be returned high before the
safe data transfer time, t
DATA
, and then held high beyond the
conversion time, t
CONV
, to avoid generation of the busy signal
indicator.
After the conversion is complete, the AD7949 enters the
acquisition phase and power-down. When the host brings CNV
low after t
CONV
(maximum), the MSB is enabled on SDO. The
host also must enable the MSB of the CFG register at this time
(if necessary) to begin the CFG update. While CNV is low, both
a CFG update and a data readback take place. The first 14 SCK
rising edges are used to update the CFG, and the first 13 SCK
falling edges clock out the conversion results starting with
MSB − 1. The restriction for both configuring and reading is
that they both must occur before the t
DATA
time of the next conver-
sion elapses. All 14 bits of CFG[13:0] must be written, or they
are ignored. In addition, if the 14-bit conversion result is not
read back before t
DATA
elapses, it is lost.
The SDO data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the 14
th
(or 28
th
) SCK falling edge, or
when CNV goes high (whichever occurs first), SDO returns to
high impedance.
If CFG readback is enabled, the CFG register associated with the
conversion result is read back MSB first following the LSB of the
conversion result. A total of 28 SCK falling edges is required to
return SDO to high impedance if this is enabled.
MISO
MOSI
SCK
SS
CNV
FOR SPI USE CPHA = 0, CPOL = 0.
SCK
SDO
DIN
AD7949
DIGITAL HOST
07351-039
Figure 39. Connection Diagram for the AD7949 Without a Busy Indicator