Datasheet

Data Sheet AD7949
Rev. D | Page 17 of 32
Unipolar or Bipolar
Figure 25 shows an example of the recommended connection
diagram for the AD7949 when multiple supplies are available.
Bipolar Single Supply
Figure 26 shows an example of a system with a bipolar input
using single supplies with the internal reference (optional
different VIO supply). This circuit is also useful when the
amplifier/signal conditioning circuit is remotely located with
some common mode present. Note that for any input config-
uration, the INx inputs are unipolar and are always referenced
to GND (no negative voltages even in bipolar range).
For this circuit, a rail-to-rail input/output amplifier can be used;
however, the offset voltage vs. input common-mode range should
be noted and taken into consideration (1 LSB = 250 μV with
V
REF
= 4.096 V). Note that the conversion results are in twos
complement format when using the bipolar input configuration.
Refer to the AN-581 Application Note, Biasing and Decoupling
Op Amps in Single Supply Applications, at www.analog.com for
additional details about using single-supply amplifiers.
ANALOG INPUTS
Input Structure
Figure 27 shows an equivalent circuit of the input structure of
the AD7949. The two diodes, D1 and D2, provide ESD protec-
tion for the analog inputs, IN[7:0] and COM. Care must be
taken to ensure that the analog input signal does not exceed the
supply rails by more than 0.3 V because this causes the diodes
to become forward biased and to start conducting current.
These diodes can handle a forward-biased current of 130 mA
maximum. For instance, these conditions may eventually occur
when the input buffer supplies are different from VDD. In such
a case, for example, an input buffer with a short circuit, the
current limitation can be used to protect the part.
C
IN
R
IN
D1
D2
C
PIN
INx+
OR INx–
OR COM
GND
VDD
07351-027
Figure 27. Equivalent Analog Input Circuit
This analog input structure allows the sampling of the true
differential signal between INx+ and COM or INx+ and INx−.
(COM or INx− = GND ± 0.1 V or V
REF
± 0.1 V). By using these
differential inputs, signals common to both inputs are rejected,
as shown in Figure 28.
70
65
60
55
50
45
40
35
30
1
10k10
CMRR (dB)
100
1k
FREQUENCY (kHz)
07351-028
Figure 28. Analog Input CMRR vs. Frequency
During the acquisition phase, the impedance of the analog inputs
can be modeled as a parallel combination of the capacitor, C
PIN
,
and the network formed by the series connection of R
IN
and C
IN
.
C
PIN
is primarily the pin capacitance. R
IN
is typically 2.4 kΩ and
is a lumped component composed of serial resistors and the on
resistance of the switches. C
IN
is typically 27 pF and is mainly
the ADC sampling capacitor.
Selectable Low-Pass Filter
During the conversion phase, where the switches are opened,
the input impedance is limited to C
PIN
. While the AD7949 is
acquiring, R
IN
and C
IN
make a one-pole, low-pass filter that
reduces undesirable aliasing effects and limits the noise from
the driving circuitry. The low-pass filter can be programmed for
the full bandwidth or ¼ of the bandwidth with CFG[6], as
shown in Table 9. This setting changes R
IN
to 19 kΩ. Note that the
converter throughput must also be reduced by ¼ when using the
filter. If the maximum throughput is used with the bandwidth
(BW) set to ¼, the converter acquisition time, t
ACQ
, is violated,
resulting in increased THD.