Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal LFCSP 20 VQ

14-Bit, 8-Channel,

250 kSPS PulSAR ADC

Data Sheet

AD7949

Rev. D

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FEATURES

14-bit resolution with no missing codes

8-channel multiplexer with choice of inputs

Unipolar single-ended

Differential (GND sense)

Pseudobipolar

Throughput: 250 kSPS

INL/DNL: ±0.5/±0.25 LSB typical

SINAD: 85 dB @ 20 kHz

THD: −100 dB @ 20 kHz

Analog input range: 0 V to V

REF

with V

REF

up to VDD

Multiple reference types

Internal selectable 2.5 V or 4.096 V

External buffered (up to 4.096 V)

External (up to VDD)

Internal temperature sensor (TEMP)

Channel sequencer, selectable 1-pole filter, busy indicator

No pipeline delay, SAR architecture

Single-supply 2.3 V to 5.5 V operation with

1.8 V to 5.5 V logic interface

Serial interface compatible with SPI, MICROWIRE,

QSPI, and DSP

Power dissipation

2.9 mW @ 2.5 V/200 kSPS

10.8 mW @ 5 V/250 kSPS

Standby current: 50 nA

20-lead 4 mm × 4 mm LFCSP package

APPLICATIONS

Multichannel system monitoring

Battery-powered equipment

Medical instruments: ECG/EKG

Mobile communications: GPS

Power line monitoring

Data acquisition

Seismic data acquisition systems

Instrumentation

Process control

FUNCTIONAL BLOCK DIAGRAM

AD7949

REF

GND

VDD

VIO

DIN

SCK

SDO

CNV

1.8V

VDD

2.3V TO 5.5

SEQUENCER

SPI SERIAL

INTERFACE

MUX

14-BIT SAR

ADC

BAND GAP

REF

TEMP

SENSOR

REFIN

IN0

IN1

IN4

IN5

IN6

IN7

IN3

IN2

COM

0.5V TO VDD

10µF

ONE-POLE

LPF

0.5V TO VDD – 0.5V

0.1µF

07351-001

Figure 1.

Table 1. Multichannel 14-/16-Bit PulSAR® ADCs

Type Channels 250 kSPS 500 kSPS ADC Driver

14-Bit 8 AD7949 ADA4841-x

16-Bit 4 AD7682 ADA4841-x

16-Bit 8 AD7689 AD7699 ADA4841-x

GENERAL DESCRIPTION

The AD7949 is an 8-channel, 14-bit, charge redistribution

successive approximation register (SAR) analog-to-digital

converter (ADC) that operates from a single power supply, VDD.

The AD7949 contains all components for use in a multichannel,

low power data acquisition system, including a true 14-bit SAR

ADC with no missing codes; an 8-channel, low crosstalk

multiplexer that is useful for configuring the inputs as single-

ended (with or without ground sense), differential, or bipolar;

an internal low drift reference (selectable 2.5 V or 4.096 V) and

buffer; a temperature sensor; a selectable one-pole filter; and a

sequencer that is useful when channels are continuously

scanned in order.

The AD7949 uses a simple SPI interface for writing to the

configuration register and receiving conversion results. The SPI

interface uses a separate supply, VIO, which is set to the host

logic level. Power dissipation scales with throughput.

The AD7949 is housed in a tiny 20-lead LFCSP with operation

specified from −40°C to +85°C.

Summary of content (32 pages)

PAGE 1
4-Bit, 8-Channel, 250 kSPS PulSAR ADC AD7949 Data Sheet FEATURES APPLICATIONS Multichannel system monitoring Battery-powered equipment Medical instruments: ECG/EKG Mobile communications: GPS Power line monitoring Data acquisition Seismic data acquisition systems Instrumentation Process control FUNCTIONAL BLOCK DIAGRAM 0.5V TO VDD – 0.5V 0.1µF 2.3V TO 5.5V 0.5V TO VDD 10µF REFIN REF BAND GAP REF VDD 1.
PAGE 2
AD7949 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Voltage Reference Output/Input .............................................. 19 Applications ....................................................................................... 1 Power Supply............................................................................... 21 Functional Block Diagram ............................................................
PAGE 3
Data Sheet AD7949 REVISION HISTORY 3/12—Rev. C to Rev. D Changes to Figure 26 ......................................................................16 Changes to Internal Reference/Temperature Sensor Section ....19 Changes to External Reference and Internal Buffer Section .....20 Changes to Bits[5:3] Function, Table 9.........................................24 Updated Outline Dimensions ........................................................32 8/11—Rev. B to Rev. C Changes to Internal Reference Section .
PAGE 4
AD7949 Data Sheet SPECIFICATIONS VDD = 2.3 V to 5.5 V, VIO = 1.8 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted. Table 2.
PAGE 5
Data Sheet Parameter INTERNAL REFERENCE REF Output Voltage REFIN Output Voltage 7 REF Output Current Temperature Drift Line Regulation Long-Term Drift Turn-On Settling Time EXTERNAL REFERENCE Voltage Range Current Drain TEMPERATURE SENSOR Output Voltage 8 Temperature Sensitivity DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format 9 Pipeline Delay 10 VOL VOH POWER SUPPLIES VDD VIO Standby Current 11, 12 Power Dissipation Energy per Conversion TEMPERATURE RANGE 13 Specified Performance A
PAGE 6
AD7949 Data Sheet TIMING SPECIFICATIONS VDD = 4.5 V to 5.5 V, VIO = 1.8 V to VDD, all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter 1 Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions Data Write/Read During Conversion CNV Pulse Width SCK Period SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO Above 2.7 V VIO Above 2.3 V VIO Above 1.8 V CNV Low to SDO D15 MSB Valid VIO Above 2.
PAGE 7
Data Sheet AD7949 VDD = 2.3 V to 4.5 V, VIO = 1.8 V to VDD, all specifications TMIN to TMAX, unless otherwise noted. Table 4. Parameter 1 Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions Data Write/Read During Conversion CNV Pulse Width SCK Period SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V VIO Above 1.
PAGE 8
AD7949 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Analog Inputs INx, 1 COM1 REF, REFIN Supply Voltages VDD, VIO to GND VIO to VDD DIN, CNV, SCK to GND SDO to GND Storage Temperature Range Junction Temperature θJA Thermal Impedance (LFCSP) θJC Thermal Impedance (LFCSP) 1 Rating GND − 0.3 V to VDD + 0.3 V or VDD ± 130 mA GND − 0.3 V to VDD + 0.3 V −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.3 V −65°C to +150°C 150°C 47.6°C/W 4.
PAGE 9
Data Sheet AD7949 20 19 18 17 16 VDD IN3 IN2 IN1 IN0 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 PIN 1 INDICATOR AD7949 TOP VIEW (Not to Scale) 15 VIO 14 SDO 13 SCK 12 DIN 11 CNV NOTES 1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SYSTEM GROUND PLANE. 07351-004 IN4 6 IN5 7 IN6 8 IN7 9 COM 10 VDD REF REFIN GND GND Figure 4. Pin Configuration Table 6. Pin Function Descriptions Pin No.
PAGE 10
AD7949 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.0 0.5 0.5 DNL (LSB) 0 4,096 8,192 12,288 16,384 CODES –1.0 07351-005 0 259,473 250k 200k 200k 16,384 150k 150k 100k 100k 50k 50k 0 0 1 0 0 0 0 1FFD 1FFE 1FFF 2000 2001 2002 2003 0 0 07351-006 0 1FFC VREF = VDD = 2.5V 0 0 955 1FFC 1FFD 1FFE 1FFF 2000 693 0 0 0 2001 2002 2003 2004 CODE IN HEX Figure 6. Histogram of a DC Input at Code Center 07351-009 COUNTS 250k CODE IN HEX Figure 9.
PAGE 11
AD7949 90 90 85 85 80 80 SINAD (dB) 75 75 70 70 50 100 150 200 FREQUENCY (kHz) 60 0 50 100 150 200 FREQUENCY (kHz) Figure 11. SNR vs. Frequency Figure 14. SINAD vs. Frequency 88 15.5 SNR SINAD ENOB 86 15.0 130 –60 125 –65 120 –70 115 –75 14.5 82 14.0 SFDR (dB) 84 ENOB (Bits) 110 –80 SFDR 105 –85 100 –90 95 –95 THD 90 80 13.5 78 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 –100 85 –105 80 –110 75 –115 70 1.0 07351-012 13.
PAGE 12
AD7949 Data Sheet 2750 100 2.5V INTERNAL REF 4.096V INTERNAL REF INTERNAL BUFFER, TEMP ON INTERNAL BUFFER, TEMP OFF EXTERNAL REF, TEMP ON EXTERNAL REF, TEMP OFF VIO VDD CURRENT (µA) 2250 THD (dB) –80 –90 –100 = 5V, –0.5dB = 2.5V, –0.5dB = 2.5V, –10dB = 5V, –10dB –120 0 50 100 150 200 FREQUENCY (kHz) 70 60 1500 50 1250 40 1000 30 750 2.5 3.0 3.5 4.0 4.5 20 5.5 5.0 VDD SUPPLY (V) Figure 17. THD vs. Frequency Figure 20. Operating Currents vs.
PAGE 13
Data Sheet AD7949 TERMINOLOGY Least Significant Bit (LSB) The LSB is the smallest increment that can be represented by a converter. For an analog-to-digital converter with N bits of resolution, the LSB expressed in volts is LSB (V) = VREF 2N Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition.
PAGE 14
AD7949 Data Sheet THEORY OF OPERATION INx+ SWITCHES CONTROL MSB 8,192C 4,096C LSB 4C 2C C SW+ C BUSY REF COMP GND 8,192C 4,096C 4C 2C C CONTROL LOGIC OUTPUT CODE C MSB LSB SW– 07351-023 CNV INx– OR COM Figure 23. ADC Simplified Schematic OVERVIEW CONVERTER OPERATION The AD7949 is an 8-channel, 14-bit, charge redistribution successive approximation register (SAR) analog-to-digital converter (ADC).
PAGE 15
Data Sheet AD7949 TRANSFER FUNCTIONS 011...111 111...111 011...110 011...101 111...110 111...101 The ideal transfer characteristic for the AD7949 is shown in Figure 24 and for both unipolar and bipolar ranges with the internal 4.096 V reference. 100...010 000...010 100...001 000...001 100...000 000...000 –FSR –FSR + 1LSB –FSR + 0.5LSB +FSR – 1LSB +FSR – 1.
PAGE 16
AD7949 Data Sheet TYPICAL CONNECTION DIAGRAMS 5V 100nF 100nF 10µF2 V+ REF REFIN VDD 1.8V TO VDD 100nF VIO 0V TO VREF ADA4841-x 3 IN0 V– V+ DIN MOSI SCK SCK SDO MISO CNV SS IN[7:1] AD7949 0V TO VREF ADA4841-x 3 V– 0V OR VREF /2 COM NOTES 1. INTERNAL REFERENCE SHOWN. SEE VOLTAGE REFERENCE OUTPUT/INPUT SECTION FOR REFERENCE SELECTION. 2. CREF IS USUALLY A 10µF CERAMIC CAPACITOR (X5R). 3. SEE THE DRIVER AMPLIFIER CHOICE SECTION FOR ADDITIONAL RECOMMENDED AMPLIFIERS. 4.
PAGE 17
Data Sheet AD7949 Unipolar or Bipolar 70 Figure 25 shows an example of the recommended connection diagram for the AD7949 when multiple supplies are available. 65 60 Bipolar Single Supply ANALOG INPUTS Input Structure Figure 27 shows an equivalent circuit of the input structure of the AD7949. The two diodes, D1 and D2, provide ESD protection for the analog inputs, IN[7:0] and COM. Care must be taken to ensure that the analog input signal does not exceed the supply rails by more than 0.
PAGE 18
AD7949 Data Sheet Figure 29 shows the different methods for configuring the analog inputs with the configuration register, CFG[12:10]. Refer to the Configuration Register, CFG, section for more details. The analog inputs can be configured as • • • • Figure 29A, single-ended referenced to system ground; CFG[12:10] = 1112. In this configuration, all inputs (IN[7:0]) have a range of GND to VREF. Figure 29B, bipolar differential with a common reference point; COM = VREF/2; CFG[12:10] = 0102.
PAGE 19
Data Sheet AD7949 DRIVER AMPLIFIER CHOICE VOLTAGE REFERENCE OUTPUT/INPUT Although the AD7949 is easy to drive, the driver amplifier must meet the following requirements: The AD7949 allows the choice of a very low temperature drift internal voltage reference, an external reference, or an external buffered reference.   The noise generated by the driver amplifier must be kept as low as possible to preserve the SNR and transition noise performance of the AD7949.
PAGE 20
AD7949 Data Sheet External Reference and Internal Buffer Reference Decoupling For improved drift performance, an external reference can be used with the internal buffer, as shown in Figure 31. The external source is connected to REFIN, the input to the on-chip unity gain buffer, and the output is produced on the REF pin. An external reference can be used with the internal buffer with or without the temperature sensor enabled. Refer to Table 9 for register details.
PAGE 21
Data Sheet AD7949 POWER SUPPLY SUPPLYING THE ADC FROM THE REFERENCE The AD7949 uses two power supply pins: an analog and digital core supply (VDD) and a digital input/output interface supply (VIO). VIO allows direct interface with any logic between 1.8 V and VDD. To reduce the supplies needed, the VIO and VDD pins can be tied together. The AD7949 is independent of power supply sequencing between VIO and VDD.
PAGE 22
AD7949 Data Sheet DIGITAL INTERFACE The AD7949 uses a simple 4-wire interface and is compatible with SPI, MICROWIRE™, QSPI™, digital hosts, and DSPs, for example, Blackfin® ADSP-BF53x, SHARC®, ADSP-219x, and ADSP-218x. The interface uses the CNV, DIN, SCK, and SDO signals and allows CNV, which initiates the conversion, to be independent of the readback timing. This is useful in low jitter sampling or simultaneous sampling applications.
PAGE 23
Data Sheet AD7949 READING/WRITING SPANNING CONVERSION, ANY SPEED HOST When reading/writing spanning conversion, the data access starts at the current acquisition (n) and spans into the conversion (n). Conversion results are for the previous (n − 1) conversion, and writing the CFG register is for the next (n + 1) acquisition and conversion. Similar to reading/writing during conversion, reading/writing should only occur up to tDATA.
PAGE 24
AD7949 Data Sheet • • • The register can be written to during conversion, during acquisition, or spanning acquisition/conversion, and is updated at the end of conversion, tCONV (maximum). There is always a one deep delay when writing the CFG register. Note that, at power-up, the CFG register is undefined and two dummy conversions are required to update the register. To preload the CFG register with a factory setting, hold DIN high for two conversions. Thus CFG[13:0] = 0x3FFF.
PAGE 25
Data Sheet AD7949 When CNV is brought low after EOC, SDO is driven from high impedance to the MSB. Falling SCK edges clock out bits starting with MSB − 1. GENERAL TIMING WITHOUT A BUSY INDICATOR Figure 36 details the timing for all three modes: read/write during conversion (RDC), read/write after conversion (RAC), and read/write spanning conversion (RSC). Note that the gating item for both CFG and data readback is at the end of conversion (EOC). At EOC, if CNV is high, the busy indicator is disabled.
PAGE 26
AD7949 Data Sheet generation requires either a high impedance or a remaining bit high-to-low transition. Because most SPI hosts are usually limited to 8-bit or 16-bit bursts, this should not be an issue. Additional clocks are not a concern because SDO remains high impedance after the 15th falling edge. GENERAL TIMING WITH A BUSY INDICATOR Figure 37 details the timing for all three modes: read/write during conversion (RDC), read/write after conversion (RAC), and read/write spanning conversion (RSC).
PAGE 27
Data Sheet AD7949 Busy Indicator section for more details. The sequencer can also be used with the busy indicator and details for these timings can be found in the General Timing with a Busy Indicator section and the Read/Write Spanning Conversion with a Busy Indicator section. CHANNEL SEQUENCER The AD7949 includes a channel sequencer useful for scanning channels in a repeated fashion. Channels are scanned as singles or pairs, with or without the temperature sensor, after the last channel is sequenced.
PAGE 28
AD7949 Data Sheet READ/WRITE SPANNING CONVERSION WITHOUT A BUSY INDICATOR This mode is used when the AD7949 is connected to any host using an SPI, serial port, or FPGA. The connection diagram is shown in Figure 39, and the corresponding timing is given in Figure 40. For the SPI, the host should use CPHA = CPOL = 0. Reading/writing spanning conversion is shown, which covers all three modes detailed in the Digital Interface section.
PAGE 29
Data Sheet AD7949 tCYC > tCONV tCONV tCONV tDATA tDATA tCNVH EOC EOC RETURN CNV HIGH FOR NO BUSY RETURN CNV HIGH FOR NO BUSY CNV tACQ (QUIET TIME) CONVERSION (n – 1) tSCK tSCKH SCK 12 13 14/ 28 CFG LSB DIN X 1 tEN END CFG (n) SDO END DATA (n – 2) 12 13 14/ 28 X X tHDIN CFG MSB – 1 BEGIN CFG (n + 1) tHSDO tDSDO tEN CFG LSB tEN END CFG (n + 1) SEE NOTE MSB LSB tDIS 2 tSDIN CFG MSB X tDIS UPDATE (n + 1) CFG/SDO SEE NOTE tCLSCK tSCKL (QUIET TIME) CONVERSION (n) AC
PAGE 30
AD7949 Data Sheet READ/WRITE SPANNING CONVERSION WITH A BUSY INDICATOR CFG update. While CNV is low, both a CFG update and a data readback take place. The first 14 SCK rising edges are used to update the CFG register, and the first 14 SCK falling edges clock out the conversion results starting with the MSB. The restriction for both configuring and reading is that they both occur before the tDATA time elapses for the next conversion. All 14 bits of CFG[13:0] must be written or they are ignored.
PAGE 31
Data Sheet AD7949 APPLICATION HINTS LAYOUT The printed circuit board (PCB) that houses the AD7949 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7949, with all its analog signals on the left side and all its digital signals on the right side, eases this task. Avoid running digital lines under the device because these couple noise onto the die unless a ground plane under the AD7949 is used as a shield.
PAGE 32
AD7949 Data Sheet OUTLINE DIMENSIONS 4.10 4.00 SQ 3.90 0.60 MAX 0.60 MAX 16 PIN 1 INDICATOR 20 15 1 PIN 1 INDICATOR 3.75 BSC SQ 0.50 BSC 2.65 2.50 SQ 2.35 EXPOSED PAD (BOTTOM VIEW) 5 11 1.00 0.85 0.80 SEATING PLANE 12° MAX 0.50 0.40 0.30 0.80 MAX 0.65 TYP 0.30 0.23 0.18 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 6 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.