Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External MSOP 10

14-Bit, 500 kSPS

PulSAR ADC in MSOP

AD7946

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

14-bit resolution with no missing codes

Throughput: 500 kSPS

INL: ±0.4 LSB typical, ±1 LSB maximum (±0.0061% of FSR)

SINAD: 85 dB @ 20 kHz

THD: −100 dB @ 20 kHz

Pseudo differential analog input range

0 V to REF with REF up to VDD

No pipeline delay

Single-supply 5 V operation with

1.8 V/2.5 V/3 V/5 V logic interface

Serial interface, SPI/QSPI/MICROWIRE™/DSP compatible

Daisy-chain multiple ADCs and BUSY indicator

Power dissipation

3.3 mW @ 5 V/100 kSPS

3.3 μW @ 5 V/100 SPS

Standby current: 1 nA

10-lead MSOP (MSOP-8 size) and

3 mm × 3 mm QFN (LFCSP) (SOT-23 size)

Pin-for-pin compatible with the 16-bit

AD7686

APPLICATIONS

Battery-powered equipment

Data acquisition

Instrumentation

Medical instruments

Process control

APPLICATION DIAGRAM

AD7946

REF

GND

VDD

IN+

IN–

VIO

SDI

SCK

SDO

CNV

1.8V TO VDD

3- OR 4-WIRE INTERFACE

(SPI, DAISY CHAIN, CS)

0.5

TO 5V 5

0V TO REF

04656-001

Figure 1.

GENERAL DESCRIPTION

The AD7946 is a 14-bit, charge redistribution, successive

approximation, analog-to-digital converter (ADC) that operates

from a single 5 V power supply, VDD. It contains a low power,

high speed, 14-bit sampling ADC with no missing codes, an

internal conversion clock, and a versatile serial interface port.

The part also contains a low noise, wide bandwidth, short

aperture delay track-and-hold circuit. On the CNV rising edge,

it samples an analog input IN+ between 0 V to REF with respect

to a ground sense IN−. The reference voltage, REF, is applied

externally and can be set up to the supply voltage.

Its power scales linearly with throughput.

The SPI-compatible serial interface also features the ability,

using the SDI input, to daisy-chain several ADCs on a single,

3-wire bus, or it provides an optional BUSY indicator. It is

compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate

supply VIO.

The AD7946 is housed in a 10-lead MSOP or a 10-lead QFN

(LFCSP) with operation specified from −40°C to +85°C.

Table 1. MSOP, QFN (LFCSP) 14-/16-/18-Bit PulSAR® ADC

Type 100 kSPS 250 kSPS 400 kSPS to 500 kSPS ≥1000 kSPS ADC Driver

14-Bit AD7940 AD7942

AD7946

16-Bit AD7680 AD7685

AD7686

AD7980

ADA4941

AD7683 AD7687

AD7688

AD7983

ADA4841

AD7684 AD7694 AD7693

18-Bit AD7691

AD7690

AD7982

ADA4941

AD7984

ADA4841

Pin-for-pin compatible.

Summary of content (24 pages)

PAGE 1
4-Bit, 500 kSPS PulSAR ADC in MSOP AD7946 APPLICATION DIAGRAM 0.5V TO 5V 14-bit resolution with no missing codes Throughput: 500 kSPS INL: ±0.4 LSB typical, ±1 LSB maximum (±0.0061% of FSR) SINAD: 85 dB @ 20 kHz THD: −100 dB @ 20 kHz Pseudo differential analog input range 0 V to REF with REF up to VDD No pipeline delay Single-supply 5 V operation with 1.8 V/2.5 V/3 V/5 V logic interface Serial interface, SPI/QSPI/MICROWIRE™/DSP compatible Daisy-chain multiple ADCs and BUSY indicator Power dissipation 3.
PAGE 2
AD7946 TABLE OF CONTENTS Features .............................................................................................. 1 Voltage Reference Input ............................................................ 14 Applications....................................................................................... 1 Power Supply............................................................................... 15 Application Diagram........................................................................
PAGE 3
AD7946 SPECIFICATIONS VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, REF = VDD, TA = −40°C to +85°C, unless otherwise noted. Table 2.
PAGE 4
AD7946 VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, REF = VDD, TA = −40°C to +85°C, unless otherwise noted. Table 3. Parameter REFERENCE Voltage Range Load Current SAMPLING DYNAMICS −3 dB Input Bandwidth Aperture Delay DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Pipeline Delay Conditions VOL VOH POWER SUPPLIES VDD VIO VIO Range Standby Current 1, 2 Power Dissipation ISINK = +500 μA ISOURCE = −500 μA TEMPERATURE RANGE 3 Specified Performance Min Typ 0.5 Max Unit VDD + 0.
PAGE 5
AD7946 TIMING SPECIFICATIONS TA = −40°C to +85°C, VDD = 4.5 V to 5.5 V, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated. See Figure 2 and Figure 3 for load conditions. Table 4. Parameter Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions CNV Pulse Width (CS Mode) SCK Period (CS Mode) SCK Period (Chain Mode) VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.
PAGE 6
AD7946 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5.
PAGE 7
AD7946 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VIO AD7946 9 SDI TOP VIEW (Not to Scale) 8 SCK 7 SDO 6 CNV IN+ 3 IN– 4 GND 5 REF 1 VDD 2 IN+ 3 IN– 4 GND 5 10 VIO AD7946 TOP VIEW (Not to Scale) 9 SDI 8 SCK 7 SDO 6 CNV 04656-005 10 04656-004 REF 1 VDD 2 Figure 5. 10-Lead QFN (LFCSP) Pin Configuration Figure 4. 10-Lead MSOP Pin Configuration Table 6. Pin Function Descriptions Pin No.
PAGE 8
AD7946 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.0 POSITIVE INL = +0.17LSB NEGATIVE INL = –0.26LSB 0.6 0.4 0.4 0.2 0.2 DNL (LSB) 0.6 0 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 0 4096 8192 12288 04656-009 0 –0.2 –0.8 –1.0 16384 0 4096 8192 CODE Figure 6. Integral Nonlinearity vs.
PAGE 9
AD7946 90.0 15.0 87.5 14.5 –90 14.0 SINAD THD, SFDR (dB) 85.0 ENOB (Bits) SNR ENOB 82.5 –100 THD –105 SFDR –110 13.5 2.7 3.1 3.5 3.9 4.3 4.7 5.1 13.0 5.5 –120 2.3 04656-015 80.0 2.3 04656-012 –115 2.7 3.1 REFERENCE VOLTAGE (V) 3.5 3.9 4.3 4.7 –90 REF = 5V REF = 5V 87.5 –100 THD (dB) 85.0 82.5 –110 80.0 –55 04656-013 –120 –35 –15 5 25 45 65 85 105 –130 –55 125 04656-016 SNR (dB) 5.5 Figure 15. THD, SFDR vs. Reference Voltage 90.
PAGE 10
AD7946 3 1000 VDD 500 250 VIO 0 4.50 4.75 5.00 5.25 2 1 OFFSET ERROR 0 –1 GAIN ERROR –2 –3 –55 5.50 04656-021 OFFSET AND GAIN ERROR (LSB) 750 04656-048 OPERATING CURRENT (µA) fS = 100kSPS –35 –15 Figure 18. Operating Current vs. Supply 25 45 65 85 105 125 Figure 21. Offset and Gain Error vs.
PAGE 11
AD7946 TERMINOLOGY Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (Figure 24).
PAGE 12
AD7946 THEORY OF OPERATION IN+ SWITCHES CONTROL MSB REF 8192C 4096C LSB 4C 2C C SW+ C BUSY COMP GND 8192C 4096C 4C 2C C CONTROL LOGIC OUTPUT CODE C MSB LSB SW– 04656-023 CNV IN– Figure 23. ADC Simplified Schematic The AD7946 is a fast, low power, single-supply, precise 14-bit ADC using a successive approximation architecture. The AD7946 can convert 500,000 samples per second (500 kSPS) and powers down between conversions. When operating at 100 SPS, for example, it consumes 3.
PAGE 13
AD7946 TYPICAL CONNECTION DIAGRAM Figure 25 shows an example of the recommended connection diagram for the AD7946 when multiple supplies are available. (NOTE 1) V+ 5V REF 10µF (NOTE 2) 100nF 1.8V TO VDD V+ 100nF REF 33Ω VDD VIO SDI IN+ 0V TO REF (ADA4841 OR NOTE 3) (NOTE 4) SCK AD7946 2.7nF V– 3- OR 4-WIRE INTERFACE (NOTE 5) SDO IN– CNV GND 04656-025 NOTES 1. SEE REFERENCE SECTION FOR REFERENCE SELECTION. 2. CREF IS USUALLY A 10µF CERAMIC CAPACITOR (X5R). 3.
PAGE 14
AD7946 tolerated. The THD degrades as a function of the source impedance and the maximum input frequency, as shown in Figure 28. Table 8.
PAGE 15
AD7946 POWER SUPPLY SUPPLYING THE ADC FROM THE REFERENCE The AD7946 is specified at 4.5 V to 5.5 V. It uses two power supply pins: a core supply VDD and a digital input/output interface supply VIO. VIO allows direct interface with any logic between 1.8 V and VDD. To reduce the supplies needed, the VIO and VDD can be tied together. The AD7946 is independent of power supply sequencing between VIO and VDD.
PAGE 16
AD7946 >5.2V independent of the readback timing (SDI). This is useful in low jitter sampling or simultaneous sampling applications. 100nF ADR364 100nF ADA4841 The AD7946, when in chain mode, provides a daisy chain feature using the SDI input for cascading multiple ADCs on a single data line similar to a shift register. 10µF 100nF 0V TO 4.096V 33Ω REF VDD IN+ VIO SDI AD7946 2.7nF SCK SDO IN– CNV 04656-052 GND Figure 32.
PAGE 17
AD7946 are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the 14th SCK falling edge or when CNV goes high, whichever is earlier, SDO returns to high impedance. CS MODE 3-WIRE, NO BUSY INDICATOR This mode is usually used when a single AD7946 is connected to an SPI-compatible digital host.
PAGE 18
AD7946 edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the optional 15th SCK falling edge, or when CNV goes high, whichever is earlier, SDO returns to high impedance. CS MODE 3-WIRE WITH BUSY INDICATOR This mode is usually used when a single AD7946 is connected to an SPI-compatible digital host having an interrupt input.
PAGE 19
AD7946 time and held high until the maximum conversion time to avoid the generation of the BUSY signal indicator. When the conversion is complete, the AD7946 enters the acquisition phase and powers down. Each ADC result can be read by bringing its SDI input low, which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges.
PAGE 20
AD7946 low. With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. The AD7946 then enters the acquisition phase and powers down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time.
PAGE 21
AD7946 onto SDO, and the AD7946 enters the acquisition phase and powers down. The remaining data bits stored in the internal shift register are then clocked by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 14 × N clocks are required to readback the N ADCs. The data is valid on both SCK edges.
PAGE 22
AD7946 Figure 43) SDO is driven high. This transition on SDO can be used as a BUSY indicator to trigger the data readback controlled by the digital host. The AD7946 then enters the acquisition phase and powers down. The data bits stored in the internal shift register are then clocked out, MSB first, by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge.
PAGE 23
AD7946 APPLICATION GUIDELINES LAYOUT The printed circuit board that houses the AD7946 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7946, with all its analog signals on the left side and all its digital signals on the right side, eases this task. At least one ground plane should be used. It could be common or split between the digital and analog sections.
PAGE 24
AD7946 OUTLINE DIMENSIONS 3.10 3.00 2.90 6 10 3.10 3.00 2.90 1 5 5.15 4.90 4.65 PIN 1 0.50 BSC 0.95 0.85 0.75 1.10 MAX 0.15 0.05 0.33 0.17 SEATING PLANE 0.80 0.60 0.40 8° 0° 0.23 0.08 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 47.10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 0.30 0.23 0.18 0.50 BSC 10 6 PIN 1 INDEX AREA *EXPOSED PAD (BOTTOM VIEW) 0.50 0.40 0.30 5 TOP VIEW 0.80 MAX 0.55 NOM 0.80 0.75 0.70 SEATING PLANE 1 2.