Datasheet

AD7943/AD7945/AD7948
REV. B –5–
(T
A
= T
MIN
to T
MAX
, unless otherwise noted)
Limit @ Limit @
Parameter V
DD
= +3 V to +3.6 V V
DD
= +4.5 V to +5.5 V Units Description
t
STB
2
60 40 ns min STB Pulsewidth
t
DS
15 10 ns min Data Setup Time
t
DH
35 25 ns min Data Hold Time
t
SRI
55 35 ns min SRI Data Pulsewidth
t
LD
55 35 ns min Load Pulsewidth
t
CLR
55 35 ns min CLR Pulsewidth
t
ASB
0 0 ns min Min Time Between Strobing Input Shift
Register and Loading DAC Register
t
SV
3
60 35 ns max STB Clocking Edge to SRO Data Valid Delay
NOTES
1
All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. tr and tf should not exceed 1 µs on any digital input.
2
STB mark/space ratio range is 60/40 to 40/60.
3
t
SV
is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
Specifications subject to change without notice.
t
STB
STB1,
STB2,
STB4
STB3
t
DS
t
DH
t
SRI
SRI
DB11(N)
(MSB)
DB10(N)
DB0(N)
DB0(N–1)
DB10(N–1)
LD1,
LD2,
CLR
SRO
t
SV
t
LD
, t
CLR
t
ASB
Figure 1. AD7943 Timing Diagram
TO OUTPUT
PIN
C
L
50pF
1.6mA
I
OL
+2.1V
I
OH
200mA
Figure 2. Load Circuit for Digital Output Timing Specifications
AD7943 TIMING SPECIFICATIONS
1