Datasheet

AD7942
Rev. B | Page 6 of 24
VDD = 2.3 V to 4.5 V
1
, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated, T
A
= −40°C to +85°C.
Table 4.
Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available t
CONV
0.7 3.2 μs
Acquisition Time t
ACQ
1.8 μs
Time Between Conversions t
CYC
5 μs
CNV Pulse Width (CS Mode)
t
CNVH
10 ns
SCK Period (CS Mode)
t
SCK
25 ns
SCK Period (Chain Mode) t
SCK
VIO ≥ 3 V 29 ns
VIO ≥ 2.7 V 35 ns
VIO ≥ 2.3 V 40 ns
SCK Low Time t
SCKL
12 ns
SCK High Time t
SCKH
12 ns
SCK Falling Edge to Data Remains Valid t
HSDO
5 ns
SCK Falling Edge to Data Valid Delay t
DSDO
VIO ≥ 3 V 24 ns
VIO ≥ 2.7 V 30 ns
VIO ≥ 2.3 V 35 ns
CNV or SDI Low to SDO D13 MSB Valid (CS Mode)
t
EN
VIO ≥ 2.7 V 18 ns
VIO ≥ 2.3 V 22 ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
t
DIS
25 ns
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
t
SSDICNV
30 ns
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
t
HSDICNV
0 ns
SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t
SSCKCNV
5 ns
SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t
HSCKCNV
8 ns
SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t
SSDISCK
5 ns
SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t
HSDISCK
4 ns
SDI High to SDO High (Chain Mode with Busy Indicator) t
DSDOSDI
36 ns
1
See Figure 2 and Figure 3 for load conditions.
Timing Diagrams
500µA I
OL
1.4V
TO SDO
500µA I
OH
C
L
50pF
04657-002
Figure 2. Load Circuit for Digital Interface Timing
30% VIO
70% VIO
2V OR VIO – 0.5V
1
0.8V OR 0.5V
2
0.8V OR 0.5V
2
2V OR VIO – 0.5V
1
t
DELAY
t
DELAY
NOTES
1
2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
2
0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
04657-003
Figure 3. Voltage Reference Levels for Timing