Datasheet

AD7942
Rev. B | Page 18 of 24
CS
Mode 3-Wire with Busy Indicator
This mode is most often used when a single AD7942 is
connected to an SPI-compatible digital host with an interrupt
input. The connection diagram is shown in Figure 32 and the
corresponding timing diagram is shown in Figure 33.
With SDI tied to VIO, a rising edge on CNV initiates a conver-
sion, selects the
CS
mode, and forces SDO to high impedance.
SDO is maintained in high impedance until the completion of
the conversion irrespective of the state of CNV. Prior to the
minimum conversion time, CNV can be used to select other
SPI devices, such as analog multiplexers. However, CNV must
be returned low before the minimum conversion time and held
low until the maximum conversion time to guarantee the
generation of the busy signal indicator. When the conversion
is complete, SDO goes from high impedance to low impedance.
With a pull-up on the SDO line, this transition can be used as
an interrupt signal to initiate the data reading controlled by the
digital host. The AD7942 then enters the acquisition phase and
powers down. The data bits are then clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host also using the SCK falling edge allows a faster
reading rate provided it has an acceptable hold time. After
the optional 15th SCK falling edge or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
CNV
SCK
SDOSDI
DATA IN
IRQ
CLK
CONVERT
VIO
VIO
DIGITAL HOST
AD7942
04657-032
47kΩ
Figure 32.
CS
Mode 3-Wire with Busy Indicator
Connection Diagram (SDI High)
SDO
D13 D12 D1 D0
t
DIS
SCK
123 131415
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
CNV
CONVERSION
ACQUISITION
t
CONV
t
CYC
t
CNVH
t
ACQ
ACQUISITION
SDI = 1
04657-033
Figure 33.
CS
Mode 3-Wire with Busy Indicator, Serial Interface Timing (SDI High)