Datasheet
Data Sheet AD7938/AD7939
Rev. C | Page 7 of 36
TIMING SPECIFICATIONS
V
DD
= V
DRIVE
= 2.7 V to 5.25 V, internal/external V
REF
= 2.5 V, unless otherwise noted; f
CLKIN
= 25.5 MHz, f
SAMPLE
= 1.5 MSPS; T
A
= T
MIN
to
T
MAX
, unless otherwise noted.
Table 4.
Limit at T
MIN
, T
MAX
Parameter
1
AD7938 AD7939 Unit Description
f
CLKIN
2
700 700 kHz min CLKIN frequency.
25.5 25.5 MHz max
t
QUIET
30 30 ns min Minimum time between end of read and start of next conversion; in other words, time
from when the data bus goes into three-state until the next falling edge of
CONVST
.
t
1
10 10 ns min
CONVST
pulse width.
t
2
15
15
ns min
CONVST
falling edge to CLKIN falling edge setup time.
t
3
50 50 ns max CLKIN falling edge to BUSY rising edge.
t
4
0 0 ns min
CS
to
WR
setup time.
t
5
0 0 ns min
CS
to
WR
hold time.
t
6
10 10 ns min
WR
pulse width.
t
7
10 10 ns min Data setup time before
WR
.
t
8
10 10 ns min Data hold after
WR
.
t
9
10 10 ns min New data valid before falling edge of BUSY.
t
10
0 0 ns min
CS
to
RD
setup time.
t
11
0 0 ns min
CS
to
RD
hold time.
t
12
30 30 ns min
RD
pulse width.
t
13
3
30 30 ns max Data access time after
RD
.
t
14
4
3 3 ns min Bus relinquish time after
RD
.
50 50 ns max Bus relinquish time after
RD
.
t
15
0 0 ns min HBEN to
RD
setup time.
t
16
0 0 ns min HBEN to
RD
hold time.
t
17
10 10 ns min Minimum time between reads/writes.
t
18
0
0
ns min
HBEN to
WR
setup time.
t
19
10 10 ns min HBEN to
WR
hold time.
t
20
40 40 ns max CLKIN falling edge to BUSY falling edge.
t
21
15.7 15.7 ns min CLKIN low pulse width.
t
22
7.8 7.8 ns min CLKIN high pulse width.
1
Sample tested during initial release to ensure compliance. All input signals are specified with t
RISE
= t
FALL
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of
1.6 V. All timing specifications given above are with a 25 pF load capacitance (see Figure 36, Figure 37, Figure 38, and Figure 39).
2
Minimum CLKIN for specified performance, with slower SCLK frequencies performance specifications apply typically.
3
The time required for the output to cross 0.4 V or 2.4 V.
4
t
14
is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or
discharging the 25 pF capacitor. This means that the time, t
14
, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the
bus loading.