Datasheet

Data Sheet AD7938/AD7939
Rev. C | Page 25 of 36
PARALLEL INTERFACE
The AD7938/AD7939 have a flexible, high speed, parallel
interface. This interface is 12-bits (AD7938) or 10-bits
(AD7939) wide and is capable of operating in either word
(W/
B
tied high) or byte (W/
B
tied low) mode. The
CONVST
signal is used to initiate conversions; when operating in
autoshutdown or autostandby mode, it is used to initiate
power-up.
A falling edge on the
CONVST
signal is used to initiate
conversions and it puts the ADC track-and-hold into track.
Once the
CONVST
signal goes low, the BUSY signal goes high
for the duration of the conversion. In between conversions,
CONVST
must be brought high for a minimum time of t
1
. This
must happen after the 14
th
falling edge of CLKIN; otherwise, the
conversion is aborted and the track-and-hold goes back into track.
At the end of the conversion, BUSY goes low and can be used to
activate an interrupt service routine. The
CS
and
RD
lines are
then activated in parallel to read the 12- or 10-bits of conversion
data. When power supplies are first applied to the device, a
rising edge on
CONVST
is necessary to put the track-and-hold
into track. The acquisition time of 125 ns minimum must be
allowed before
CONVST
is brought low to initiate a conversion.
The ADC then goes into hold on the falling edge of
CONVST
and back into track on the 13
th
rising edge of CLKIN after this
(see Figure 36). When operating the device in autoshutdown or
autostandby mode, where the ADC powers down at the end of
each conversion, a rising edge on the
CONVST
signal is used to
power up the device.
t
2
t
3
t
20
t
14
t
11
t
9
t
13
t
12
t
10
t
CONVERT
t
ACQUISITION
t
QUIET
t
1
12345 121314
B
A
DATA
DATAOLD DATADB0 TO DB11
DB0 TO DB11
RD
CS
INTERNAL
TRACK/HOLD
BUSY
CLKIN
CONVST
THREE-STATE
THREE-STATE
WITH CS AND RD TIED LOW
03715-004
Figure 36. AD7938/AD7939 Parallel Interface—Conversion and Read Cycle Timing in Word Mode (W/
B
= 1)