Datasheet

AD7938-6 Data Sheet
Rev. C | Page 28 of
AD7938-6 to ADSP-21065L Interface
32
Figure 43 shows a typical interface between the AD7938-6 and
the ADSP-21065L SHARC® processor. This interface is an
example of one of three DMA handshake modes. The
MS
x
control line is actually three memory select lines. Internal
ADDR
25 to 24
are decoded into
MS
3 to 0
, these lines are then
asserted as chip selects. The
DMAR
1
(DMA request 1) is used in
this setup as the interrupt to signal the end of conversion. The
rest of the interface is a standard handshaking operation.
AD7938-6*
ADSP-21065L*
WR
DB0 TO DB11
D0 TO D31
A0 TO A23
MS
X
DMAR
1
BUSY
CS
CONVST
DSP/USER SYSTEM
WR
RDRD
*
ADDITION
A
L PINS REMOVED FOR CLARITY.
ADDRESS BUS
ADDRESS BUS
DATA BUS
ADDRESS
LATCH
ADDRESS
DECODER
04751-046
Figure 43. Interfacing to the ADSP-21065L
AD7938-6 to TMS32020, TMS320C25, and TMS320C5x
Interface
Parallel interfaces between the AD7938-6 and the TMS32020,
TMS320C25, and TMS320C5x family of DSPs are shown in
Figure 44. The memory mapped address chosen for the AD7938-6
should be chosen to fall in the I/O memory space of the DSPs.
The parallel interface on the AD7938-6 is fast enough to
interface to the TMS32020 with no extra wait states. If high
speed glue logic, such as 74AS devices, is used to drive the
RD
and the
WR
lines when interfacing to the TMS320C25, then
again, no wait states are necessary. However, if slower logic is
used, data accesses may be slowed sufficiently when reading
from, and writing to, the part to require the insertion of one
wait state. Extra wait states are necessary when using the
TMS320C5x at their fastest clock speeds (see the TMS320C5x
User’s Guide for details).
Data is read from the ADC using the following instruction
IN D, ADC
where:
D is the data memory address.
ADC is the AD7938-6 address.
AD7938-6*
TMS32020/
TMS320C25/
TMS320C50*
WR
RD
DB11 TO DB0DMD0 TO DMD15
A0 TO A15
IS
READY
INT
X
BUSY
CSEN
CONVST
DSP/USER SYSTEM
TMS320C25
ONLY
R/W
STRB
*ADDITIONAL PINS OMITTED FOR CLARITY.
ADDRESS BUS
ADDRESS
DECODER
MSC
DATA BUS
04751-047
Figure 44. Interfacing to the TMS32020/TMS320C25/TMS320C5x
AD7938-6 to 80C186 Interface
Figure 45 shows the AD7938-6 interfaced to the 80C186
microprocessor. The 80C186 DMA controller provides two
independent high speed DMA channels where data transfer
can occur between memory and I/O spaces. Each data transfer
consumes two bus cycles, one cycle to fetch data and the other
to store data. After the AD7938-6 has finished a conversion, the
BUSY line generates a DMA request to Channel 1 (DRQ1).
Because of the interrupt, the processor performs a DMA read
operation that also resets the interrupt latch. Sufficient priority
must be assigned to the DMA channel to ensure that the DMA
request is serviced before the completion of the next
conversion.
AD7938-6*
80C186*
WR
DB0 TO DB11
AD0 TO AD15
A16 TO A19
ALE
DRQ1
BUSY
CS
QR
S
CONVST
MICROPROCESSOR/
USER SYSTEM
WR
RDRD
L PINS OMITTED FOR CLARITY
ADDRESS/DATA BUS
ADDRESS BUS
*
ADDITION
A
DATA BUS
ADDRESS
LATCH
ADDRESS
DECODER
04751-048
Figure 45. Interfacing to the 80C186