Datasheet

Data Sheet AD7938-6
Rev. C | Page 15 of 32
Table 10. Sequence Selection
SEQ SHDW Sequence Type
0 0
This configuration is selected when the sequence function is not used. The analog input channel selected on each
individual conversion is determined by the contents of the channel address bits, ADD2 to ADD0, in each prior write
operation. This mode of operation reflects the traditional operation of a multichannel ADC, without the sequencer function
being used, where each write to the AD7938-6 selects the next channel for conversion.
0 1
This configuration selects the shadow register for programming. The following write operation loads the data on DB0 to
DB7 to the shadow register. This programs the sequence of channels to be converted continuously after each CONVST
falling edge (see the section and ). Shadow Register Table 11
1 0
If the SEQ and SHDW bits are set in this way, the sequence function is not interrupted upon completion of the write
operation. This allows other bits in the control register to be altered between conversions while in a sequence without
terminating the cycle.
1 1
This configuration is used in conjunction with the channel address bits (ADD2 to ADD0) to program continuous
conversions on a consecutive sequence of channels from Channel 0 through to a selected final channel as determined by
the channel address bits in the control register.
Table 11. Shadow Register Bit Functions
MSB LSB
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
V
IN
7 V
IN
6 V
IN
5 V
IN
4 V
IN
3 V
IN
2 V
IN
1 V
IN
0