Datasheet

AD7933/AD7934
Rev. B | Page 28 of 32
AD7933/AD7934 to ADSP-21065L Interface
Figure 42 shows a typical interface between the AD7933/AD7934
and the
ADSP-21065L SHARC® processor. This interface is an
example of one of three DMA handshake modes. The
MS
X
control line is actually three memory select lines. Internal
ADDR
25 to 24
are decoded into
MS
3 to 0
, these lines are then
asserted as chip selects. The
DMAR
1
(DMA Request 1) is used
in this setup as the interrupt to signal the end of the conversion.
The rest of the interface is standard handshaking operation.
AD7933/
AD7934*
ADSP-21065L*
WR
DB0 TO DB11
D0 TO D31
ADDR
0
TO ADDR
23
MS
X
DMAR
1
BUSY
CS
CONVST
DSP
/
USER SYSTEM
WR
RDRD
*ADDITIONAL PINS OMITTED FOR CLARITY.
ADDRESS BUS
ADDRESS BUS
DATA BUS
ADDRESS
LATCH
ADDRESS
DECODER
03713-045
Figure 42. Interfacing to the ADSP-21065L
AD7933/AD7934 to TMS32020, TMS320C25, and
TMS320C5x Interface
Parallel interfaces between the AD7933/AD7934 and the
TMS32020, TMS320C25 and TMS320C5x family of DSPs are
shown in
Figure 43. Select the memory-mapped address for the
AD7933/AD7934 to fall in the I/O memory space of the DSPs.
The parallel interface on the AD7933/AD7934 is fast enough to
interface to the TMS32020 with no extra wait states. If high
speed glue logic, such as 74AS devices, is used to drive the
RD
and the
WR
lines when interfacing to the TMS320C25, no
wait states are necessary. However, if slower logic is used, data
accesses may be slowed sufficiently when reading from, and
writing to, the part to require the insertion of one wait state.
Extra wait states are necessary when using the TMS320C5x at
their fastest clock speeds (see the TMS320C5x User’s Guide
for details).
Data is read from the ADC using the following instruction:
IN D, ADC
where:
D is the data memory address.
ADC is the AD7933/AD7934 address.
AD7933/
AD7934*
TMS32020/
TMS320C25/
TMS320C50*
WR
RD
DB11 TO DB0DMD0 TO DMD15
A0 TO A15
IS
READY
INT
X
BUSY
CSEN
CONVST
DSP
/
USER SYSTEM
TMS320C25
ONLY
R/W
STRB
*ADDITIONAL PINS OMITTED FOR CLARITY.
ADDRESS BUS
DATA BUS
ADDRESS
DECODER
03713-046
MSC
Figure 43. Interfacing to TMS32020/TMS320C25/TMS320C5x
AD7933/AD7934 to 80C186 Interface
Figure 44 shows the AD7933/AD7934 interfaced to the 80C186
microprocessor. The 80C186 DMA controller provides two
independent, high speed DMA channels where data transfers
can occur between memory and I/O spaces. Each data transfer
consumes two bus cycles, one cycle to fetch data and the other
to store data. After the AD7933/AD7934 finish a conversion,
the BUSY line generates a DMA request to Channel 1 (DRQ1).
Because of the interrupt, the processor performs a DMA read
operation, which also resets the interrupt latch. Sufficient
priority must be assigned to the DMA channel to ensure that
the DMA request is serviced before the completion of the next
conversion.
AD7933/
AD7934*
80C186*
WR
DB0 TO DB11
AD0 TO AD15
A16 TO A19
ALE
DRQ1
BUSY
CS
QR
S
CONVST
MICROPROCESSOR/
USER SYSTEM
WR
RDRD
*
ADDITIONAL PINS OMITTED FOR CLARITY.
ADDRESS/DATA BUS
ADDRESS BUS
DATA BUS
ADDRESS
LATCH
ADDRESS
DECODER
03713-047
Figure 44. Interfacing to the 80C186