Datasheet

Data Sheet AD7927
Rev. D | Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
DIN
AGND
REF
IN
AV
DD
AV
DD
SCLK
V
IN
6
V
IN
7
AGND
20
19
18
17
16
15
14
13
12
11
V
DRIVE
DOUT
AGND
V
IN
2
V
IN
1
V
IN
0
V
IN
5
V
IN
4
V
IN
3
AGND
AD7927
TOP VIEW
(Not to Scale)
03088-003
CS
Figure 3. 20-Lead TSSOP Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 SCLK
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is
also used as the clock source for the AD7927 conversion process.
2 DIN
Data In. Logic input. Data to be written to the AD7927 control register is provided on this input and is clocked
into the register on the falling edge of SCLK (see the Control Register section).
3
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the
AD7927 and framing the serial data transfer.
4, 8, 17, 20 AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7927. All analog input signals
and any external reference signal should be referred to this AGND voltage. All AGND pins should be
connected together.
5, 6 AV
DD
Analog Power Supply Input. The AV
DD
range for the AD7927 is from 2.7 V to 5.25 V. For the 0 V to 2 × REF
IN
range, AV
DD
should be from 4.75 V to 5.25 V.
7 REF
IN
Reference Input for the AD7927. An external reference must be applied to this input. The voltage range for
the external reference is 2.5 V ±1% for specified performance.
16 to 9 V
IN
0 to V
IN
7
Analog Input 0 through Analog Input 7. Eight single-ended analog input channels that are multiplexed into
the on-chip track-and-hold. The analog input channel to be converted is selected by using the address bits
(ADD2 through ADD0) of the control register. ADD2 through ADD0, in conjunction with the SEQ and
SHADOW bits, allow the sequencer to be programmed. The input range for all input channels can extend
from 0 V to REF
IN
or 0 V to 2 × REF
IN
, as selected via the RANGE bit in the control register. Any unused input
channels should be connected to AGND to avoid noise pickup.
18 DOUT
Data Out. Logic output. The conversion result from the AD7927 is provided on this output as a serial data
stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7927
consists of two leading zeros, two address bits indicating which channel the conversion result corresponds to,
followed by the 12 bits of conversion data (MSB first). The output coding may be selected as straight binary or
twos complement via the CODING bit in the control register.
19 V
DRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial interface of
the AD7927 operates.