Datasheet

Data Sheet AD7927
Rev. D | Page 23 of 28
SCLK
DOUT
DIN
ZERO
3 IDENTIFICATION BITS
C
CS
t
2
t
3
t
9
THREE-
STATE
V
IN
0
SEQUENCE 1 SEQUENCE 2
V
IN
1V
IN
2V
IN
3V
IN
4V
IN
5V
IN
5V
IN
6V
IN
7
t
4
t
6
t
10
t
CONVERT
t
7
t
5
t
8
t
11
THREE-STATE
DB0DB1DB2DB10DB11ADD0ADD1ADD2
1615141354321
03088-027
Figure 27. Writing to Shadow Register Timing Diagram
11
SCLK
DOUT
POWER-UP
DIN
VAL I D DATAVAL I D DATA
16 16
1
16
t
QUIET
MINIMUM
t
CYCLE
5µs MINIMUM
CS
03088-028
Figure 28. General Timing Diagram