Datasheet

Data Sheet AD7923
Rev. D | Page 23 of 24
APPLICATION HINTS
GROUNDING AND LAYOUT
The AD7923 has very good immunity to noise on the power
supplies as can be seen by the PSRR vs. supply ripple frequency
plot, Figure 6. However, care should still be taken in grounding
and layout.
The printed circuit board that houses the AD7923 should be
designed such that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be separated easily. A minimum
etch technique is generally best for ground planes since it gives
the best shielding. All three AGND pins of the AD7923 should
be sunk into the AGND plane. Digital and analog ground
planes should be joined at only one place. If the AD7923 is in a
system where multiple devices require an AGND to DGND
connection, the connection should still be made at one point
only, a star ground point that should be established as close as
possible to the AD7923.
Avoid running digital lines under the device since they couple
noise onto the die. The analog ground plane should be allowed
to run under the AD7923 to avoid noise coupling. The power
supply lines to the AD7923 should use as large a trace as
possible to provide low impedance paths and reduce the effects
of glitches on the power supply line. Fast switching signals, like
clocks, should be shielded with digital ground to avoid radiating
noise to other sections of the board, and clock signals should
never be run near the analog inputs. Avoid crossover of digital
and analog signals. Traces on opposite sides of the board should
run at right angles to each other. This reduces the effects of
feedthrough through the board. A microstrip technique is by far
the best technique, but is not always possible with a double-
sided board. In this technique, the component side of the board
is dedicated to ground planes, while signals are placed on the
solder side.
Good decoupling is also important. All analog supplies should
be decoupled with 10 µF tantalum in parallel with 0.1 µF capa-
citors to AGND. To achieve the best results from these
decoupling components, they must be placed as close as pos-
sible to the device, ideally right up against the device. The 0.1
µF capacitors should have low effective series resistance (ESR)
and low effective series inductance (ESI), such as the common
ceramic types or surface mount types, which provide a low
impedance path to ground at high frequencies to handle
transient currents from internal logic switching.