Datasheet

AD7912/AD7922
Rev. 0 | Page 8 of 32
TIMING EXAMPLES
Figure 6 and Figure 7 show some of the timing parameters from
the Timing Specifications section.
Timing Example 1
As shown in Figure 7, when f
SCLK
= 18 MHz and the throughput
is 1 MSPS, the cycle time is
t
2
+ 12.5(1/f
SCLK
) + t
ACQ
= 1 µs
With t
2
= 10 ns minimum, then t
ACQ
is 295 ns, which satisfies the
requirement of 290 ns for t
ACQ
.
In Figure 7, t
ACQ
is comprised of 2.5(1/f
SCLK
) + t
10
+ t
QUIET
, where
t
10
= 30 ns maximum. This allows a value of 126 ns for t
QUIET
,
satisfying the minimum requirement of 30 ns.
Timing Example 2
The AD7922 can also operate with slower clock frequencies. As
shown in Figure 7, when f
SCLK
= 5 MHz and the throughput rate
is 315 kSPS, the cycle time is
t
2
+ 12.5(1/f
SCLK
) + t
ACQ
= 3.17 µs
With t
2
= 10 ns minimum, then t
ACQ
is 664 ns, which satisfies the
requirement of 290 ns for t
ACQ
.
In Figure 7, t
ACQ
is comprised of 2.5(1/f
SCLK
) + t
10
+ t
QUIET
, where
t
10
= 30 ns maximum. This allows a value of 134 ns for t
QUIET
,
satisfying the minimum requirement of 30 ns.
In this example, as with other slower clock values, the signal
might already be acquired before the conversion is complete,
but it is still necessary to leave 30 ns minimum t
QUIET
between
conversions. In this example, the signal should be fully acquired
at approximately point C in Figure 7.
04351-0-006
ZERO
X
12345 13141516
X CHN STY X X X XX
CHN MOD DB11 DB10 DB2 DB1 DB0Z
t
2 t
6
t
4
t
8
t
9
t
3
t
7
t
5
t
10
t
1
t
QUIET
t
CONVERT
SCLK
CS
DOUT
THREE-STATE THREE-STATE
DIN
B
Figure 6. AD7922 Serial Interface Timing Diagram
04351-0-007
12345 13141516
t
QUIET
t
ACQUISITION
1/THROUGHPUT
12.5(1/f
SCLK
)
t
CONVERT
BC
SCLK
CS
t
10
t
2
Figure 7. Serial Interface Timing Example