Datasheet

AD7910/AD7920
Rev. C | Page 7 of 24
TIMING EXAMPLES
Figure 3 and Figure 4 show some of the timing parameters from
Table 3.
TIMING EXAMPLE 1
From Figure 4, having f
SCLK
= 5 MHz and a throughput rate of
250 kSPS gives a cycle time of t
2
+ 12.5(1/f
SCLK
) + t
ACQ
= 4 μs.
With t
2
= 10 ns min, this leaves t
ACQ
to be 1.49 μs. This 1.49 μs
satisfies the requirement of 250 ns for t
ACQ
. From Figure 4, t
ACQ
comprises 2.5(1/f
SCLK
) + t
8
+ t
QUIET
, where t
8
= 36 ns max. This
allows a value of 954 ns for t
QUIET
, satisfying the minimum
requirement of 50 ns.
TIMING EXAMPLE 2
The AD7920 can also operate with slower clock frequencies.
From
Figure 4, having f
SCLK
= 3.4 MHz and a throughput rate of
150 kSPS gives a cycle time of t
2
+ 12.5(1/f
SCLK
) + t
ACQ
= 6.66 μs.
With t
2
= 10 ns min, this leaves t
ACQ
to be 2.97 μs. This 2.97 μs
satisfies the requirement of 250 ns for t
ACQ
. From Figure 4, t
ACQ
comprises 2.5(1/f
SCLK
) + t
8
+ t
QUIET
, t
8
= 36 ns max. This allows a
value of 2.19 μs for t
QUIET
, satisfying the minimum requirement
of 50 ns. As in this example and with other slower clock values,
the signal may already be acquired before the conversion is
complete, but it is still necessary to leave 50 ns minimum t
QUIET
between conversions. In this example, the signal should be fully
acquired at approximately Point C in
Figure 4.
CS
SCLK
SDATA
t
2
t
6
t
3
t
4
t
7
t
5
t
8
t
CONVERT
t
QUIET
ZERO ZERO ZERO DB11 DB10 DB2 DB1 DB0
B
THREE-STATETHREE-
STATE
Z
4 LEADING ZEROS
12345 13141516
t
1
02976-003
Figure 3. AD7920 Serial Interface Timing Diagram
CS
S
CLK
t
2
t
CONVERT
B
12345 13141516
C
t
8
t
QUIET
t
ACQ
12.5(1/f
SCLK
)
1/THROUGHPUT
02976-004
Figure 4. Serial Interface Timing Example