Datasheet

AD7910/AD7920
Rev. C | Page 15 of 24
AD7910/
AD7920
V
DD
V
IN
SERIAL
INTERFACE
0V TO V
DD
INPUT
μ C/ μ P
GND
SCLK
SDATA
CS
0.1 μ F10 μ F
1 μ F
TANT
0.1 μ F
680nF
3V
5V
SUPPLY
1.2mA
REF193
02976-017
Figure 17. REF193 as Power Supply
Table 6 provides typical performance data with various
references used as a V
DD
source for a 100 kHz input tone at
room temperature, under the same setup conditions.
Table 6. AD7920 Typical Performance for Various Voltage
References IC
Reference Tied to V
DD
AD7920 SNR Performance (dB)
AD780 @ 3 V 72.65
REF193 72.35
AD780 @ 2.5 V 72.5
REF192 72.2
REF43 72.6
ANALOG INPUT
Figure 18 shows an equivalent circuit of the analog input
structure of the AD7910/AD7920. The two diodes, D1 and D2,
provide ESD protection for the analog input. Care must be
taken to ensure that the analog input signal never exceeds the
supply rails by more than 300 mV. This causes these diodes to
become forward biased and start conducting current into the
substrate. The maximum current these diodes can conduct
without causing irreversible damage to the parties is 10 mA.
Capacitor C1 in
Figure 18 is typically about 6 pF and can be
attributed primarily to pin capacitance. Resistor R1 is a lumped
component made up of the on resistance of a switch. This
resistor is typically about 100 Ω. Capacitor C2 is the ADC
sampling capacitor and has a capacitance of 20 pF typically. For
ac applications, removing high frequency components from the
analog input signal is recommended by use of a band-pass filter
on the relevant analog input pin. In applications where
harmonic distortion and signal-to-noise ratio are critical, the
analog input should be driven from a low impedance source.
Large source impedances significantly affect the ac performance
of the ADC. This can necessitate the use of an input buffer
amplifier. The choice of the op amp is a function of the
particular application.
C1
6pF
C2
20pF
R1
D1
D2
CONVERSION PHASE—SWITCH OPEN
TRACK PHASE—SWITCH CLOSED
V
DD
V
IN
02976-018
Figure 18. Equivalent Analog Input Circuit
Table 7 provides some typical performance data with various op
amps used as the input buffer for a 100 kHz input tone at room
temperature, under the same setup conditions.
Table 7. AD7920 Typical Performance for Various Input
Buffers, V
DD
= 3 V
Op Amp in the Input Buffer AD7920 SNR Performance (dB)
AD711 72.3
AD797 72.5
AD845 71.4
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance depends on the amount of total harmonic
distortion (THD) that can be tolerated. The THD increases as
the source impedance increases, and performance degrades (see
Figure 12).
DIGITAL INPUTS
The digital inputs applied to the AD7910/AD7920 are not limited
by the maximum ratings that limit the analog input. Instead, the
digital inputs applied can go to 7 V and are not restricted by the
V
DD
+ 0.3 V limit as on the analog input. For example, if the
AD7910/AD7920 were operated with a V
DD
of 3 V, then 5 V logic
levels could be used on the digital inputs. However, it is important
to note that the data output on SDATA still have 3 V logic levels
when V
DD
= 3 V. Another advantage of SCLK and
CS
not being
restricted by the V
DD
+ 0.3 V limit is that power supply
sequencing issues are avoided. If
CS
or SCLK is applied before
V
DD
, there is no risk of latch-up as there would be on the analog
inputs if a signal greater than 0.3 V were applied prior to V
DD
.