Datasheet

AD7908/AD7918/AD7928
Rev. D | Page 11 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
AD7908/
AD7918/
AD7928
TOP VIEW
(Not to Scale)
SCLK
20
2
DIN
19
3
CS
DOUT
18
4
AGND
AGND
AGND
AGND
17
5
AV
DD
AV
DD
V
DRIVE
REF
IN
16
615
714
813
9
V
IN
7
V
IN
6
V
IN
0
V
IN
1
V
IN
2
V
IN
3
V
IN
4
V
IN
5
12
10 11
03089-003
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 SCLK
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also
used as the clock source for the conversion process of the AD7908/AD7918/AD7928.
2 DIN
Data In. Logic input. Data to be written to the control register of the AD7908/AD7918/AD7928 is provided on
this input and is clocked into the register on the falling edge of SCLK (see the Control Register section).
3
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the
AD7908/AD7918/AD7928, and also frames the serial data transfer.
4, 8, 17, 20 AGND
Analog Ground. This is the ground reference point for all analog circuitry on the AD7908/AD7918/AD7928. All
analog input signals and any external reference signal should be referred to this AGND voltage. All AGND pins
should be connected together.
5, 6 AV
DD
Analog Power Supply Input. The AV
DD
range for the AD7908/AD7918/AD7928 is from 2.7 V to 5.25 V. For the 0 V
to 2 × REF
IN
range, AV
DD
should be from 4.75 V to 5.25 V.
7 REF
IN
Reference Input for the AD7908/AD7918/AD7928. An external reference must be applied to this input. The
voltage range for the external reference is 2.5 V ± 1% for specified performance.
16 to 9 V
IN
0 to V
IN
7
Analog Input 0 through Analog Input 7. These are eight single-ended analog input channels that are
multiplexed into the on-chip track-and-hold. The analog input channel to be converted is selected by using
Address Bit ADD2 through Address Bit ADD0 of the control register. The address bits, in conjunction with the
SEQ and SHADOW bits, allow the sequencer to be programmed. The input range for all input channels can
extend from 0 V to REF
IN
or 0 V to 2 × REF
IN
as selected via the RANGE bit in the control register. Any unused
input channels must be connected to AGND to avoid noise pickup.
18 DOUT
Data Out. Logic output. The conversion result from the AD7908/AD7918/AD7928 is provided on this output as
a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the
AD7908 consists of one leading zero, three address bits indicating which channel the conversion result
corresponds to, followed by the eight bits of conversion data, followed by four trailing zeros, provided MSB
first; the data stream from the AD7918 consists of one leading zero, three address bits indicating which
channel the conversion result corresponds to, followed by the 10 bits of conversion data, followed by two
trailing zeros, also provided MSB first; the data stream from the AD7928 consists of one leading zero, three
address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of
conversion data, provided MSB first. The output coding can be selected as straight binary or twos complement
via the CODING bit in the control register.
19 V
DRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial interface of
the AD7908/AD7918/AD7928 operates.