Datasheet
REV. A
AD7899
–4–
TIMING CHARACTERISTICS
1, 2
A, B and S
Parameter Versions Unit Test Conditions/Comments
t
CONV
2.2 µs max Conversion Time, Internal Clock
2.46 µs max CLKIN = 6.5 MHz
t
ACQ
0.3 µs max Acquisition Time
t
EOC
120 ns min EOC Pulsewidth
180 ns max
t
WAKE-UP
– External V
REF
5
2 µs max STBY Rising Edge to CONVST Rising Edge
(See Standby Mode Operation)
t
1
35 ns min CONVST Pulsewidth
t
2
70 ns min CONVST Rising Edge to BUSY Rising Edge
Read Operation
t
3
0 ns min CS to RD Setup Time
t
4
0 ns min CS to RD Hold Time
t
5
35 ns min Read Pulsewidth
t
6
3
35 ns max Data Access Time after Falling Edge of RD, V
DRIVE
= 5 V
40 ns max Data Access Time after Falling Edge of RD, V
DRIVE
= 3 V
t
7
4
5 ns min Bus Relinquish Time after Rising Edge of RD
30 ns max
t
8
0 ns min BUSY Falling Edge to RD Delay
External Clock
t
9
0 ns min CLKIN to CONVST Rising Edge Setup Time
t
10
20 ns min CLKIN to CONVST Rising Edge Hold Time
t
11
100 ns min CONVST Rising Edge to CLK Falling Edge
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of V
DRIVE
) and timed from a voltage level of V
DRIVE
/2.
2
See Figures 5, 6, 7, and 8.
3
Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.0 V.
4
These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
5
Refer to the Standby Mode Operation section.
Specifications subject to change without notice.
(V
DD
= 5 V ⴞ 5%, AGND = DGND = 0 V, V
REF
= Internal, Clock = Internal; All specifications T
MIN
to T
MAX
and valid for V
DRIVE
= 3 V ⴞ 5% and 5 V ⴞ 5% unless otherwise noted.)
1.6mA
1.6V
400A
50pF
TO
OUTPUT
PIN
Figure 1. Load Circuit for Access Time and Bus Relinquish Time