Datasheet

AD7896
–3–
Test Conditions/
Parameter A Version
1
B Version J Version S Version Unit Comments
POWER REQUIREMENTS
V
DD
2.7/5.5 2.7/5.5 2.7/5.5 2.7/5.5 V min/max
I
DD
4444mA max Digital Input @ DGND,
V
DD
= 2.7 V to 3.6 V
5555mA max Digital Inputs @ DGND,
V
DD
= 5 V ± 10%
Power Dissipation 10.8 10.8 10.8 10.8 mW max V
DD
= 2.7 V, Typically 9 mW
Power-Down Mode Digital Inputs @ DGND
I
DD
@ 25°C 555 typ5µA max V
DD
= 2.7 V to 3.6 V
T
MIN
to T
MAX
15 15 75 75 µA max V
DD
= 2.7 V to 3.6 V
I
DD
@ 25°C50505050µA max V
DD
= 5 V ± 10%
T
MIN
to T
MAX
150 150 500 500 µA max V
DD
= 5 V ± 10%
Power Dissipation @ 25°C 13.5 13.5 13.5 13.5 µW max V
DD
= 2.7 V
NOTES
1
Temperature ranges are as follows: A, B Versions: –40°C to +85°C; J Version: 0°C to +70°C; S Version: –55°C to +125°C.
2
Applies to Mode 1 operation. See the section on Operating Modes.
3
See Terminology.
4
Sample tested @ 25°C to ensure compliance.
5
This 14 µs includes the wake-up time from standby. This wake-up time is timed from the rising edge of CONVST, whereas conversion is timed from the falling edge
of CONVST , for narrow CONVST pulsewidth the conversion time is effectively the wake-up time plus conversion time, hence 14 µs. This can be seen from Figure 3.
Note that if the CONVST pulsewidth is greater than 6 µs, the effective conversion time will increase beyond 14 µs.
Specifications subject to change without notice.
Parameter A, B Versions J Version S Version Unit Test Conditions/Comments
t
1
40 40 40 ns min CONVST Pulsewidth
t
2
40
2
40
2
45
2
ns min SCLK High Pulsewidth
t
3
40
2
40
2
45
2
ns min SCLK Low Pulsewidth
t
4
Data Access Time after Falling Edge of SCLK
60
3
60
3
70
3
ns max V
DD
= 5 V ± 10%
100
3
100
3
110
3
ns max V
DD
= 2.7 V to 3.6 V
t
5
10 10 10 ns min Data Hold Time after Falling Edge of SCLK
t
6
50
4
50
4
50
4
ns max Bus Relinquish Time after Falling Edge of SCLK
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.4 V.
2
The SCLK maximum frequency is 10 MHz. Care must be taken when interfacing to account for the data access time, t
4
, and the setup time required for the user’s
processor. These two times will determine the maximum SCLK frequency that the user’s system can operate with. See Serial Interface section for more information.
3
Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2 V.
4
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
6
, quoted in the timing characteristics is the true bus relinquish time
of the part and as such is independent of external bus loading capacitances.
TIMING CHARACTERISTICS
1
(V
DD
= 2.7 V to 5.5 V, AGND = DGND = 0 V)
1.6V
1.6mA
400␮A
50pF
TO
OUTPUT
PIN
Figure 1. Load Circuit for Access Time and Bus
Relinquish Time
Rev. D