Datasheet

AD7892
–12–
REV. C
MICROPROCESSOR INTERFACING
The AD7892 features both high speed parallel and serial inter-
faces, allowing considerable flexibility in interfacing to micro-
processor systems. To obtain optimum performance from the
part, data should not be read during conversion and this limits
the achievable throughput rate in serial mode to 400 kSPS for
the AD7892-3.
Figures 6, 7 and 9 show some typical interface circuits between
the AD7892 and popular DSP processors. Figure 8 shows an
interface between the part and a gate array or ASIC where data
is clocked into the ASIC by the AD7892 itself at the end of
conversion. In all cases, the CONVST signal is generated from
an external timer to ensure equidistant sampling.
AD7892 to ADSP-2101 Interface
Figure 6 shows a parallel interface between the AD7892 and the
ADSP-2101 DSP processor. CONVST starts conversion and at
the end of conversion the falling edge of the EOC output pro-
vides an interrupt request to the ADSP-2101.
ADSP-2101
AD7892
ADDRESS DECODE
LOGIC
CONVST
CS
RD
DB11–DB0
DATA BUS
ADDRESS BUS
DMA13–DMA0
DMD15–DMD0
IRQn
DMS
RD
EOC
EN
TIMER
Figure 6. AD7892 to ADSP-2101
AD7892 to TMS320C25 Interface
Figure 7 shows a parallel interface between the AD7892 and the
TMS320C25 DSP processor. CONVST starts conversion and
at the end of conversion the falling edge of the EOC output
provides an interrupt request to the TMS320C25.
TMS320C25
AD7892
ADDRESS DECODE
LOGIC
CONVST
CS
RD
DATA BUS
ADDRESS BUSA15–A0
D15–D0
STRB
IS
INT
EOC
EN
TIMER
G2
READY
MSC
R/W
DB11–DB0
Figure 7. AD7892 to TMS320C25 Interface
EOC Pulse Provides CS and RD
Figure 8 shows a parallel interface between the AD7892 and a
gate array or ASIC. CONVST starts conversion and at the end
of conversion the falling edge of the EOC output provides the
CS and RD pulse to latch data out of the AD7892 and into the
gate array/ASIC. This scheme allows for the fastest possible
throughput rate with the part as no time is lost in interrupt
service routines and as soon as data is available from the part it
is transferred out of it.
GATE
ARRAY/ASIC
AD7892
CONVST
CS
RD
DB11–DB0
DATA BUS
DB11–DB0
ENABLE
EOC
TIMER
Figure 8. AD7892 to Gate Array/ASIC Interface
AD7892 to DSP56000 Interface
Figure 9 shows a serial interface between the AD7892 and the
DSP56000 DSP processor. CONVST starts conversion and at
the end of conversion the falling edge of the EOC output pro-
vides an interrupt request to the DSP56000.
AD7892
CONVST
RFS
SDATA
EOC
TIMER
SCLK
DSP56000
SC1
SRD
IRQA
SCK
Figure 9. AD7892 to DSP56000 Interface