Datasheet

AD7888
–4–
Limit at T
MIN
, T
MAX
(A, B Versions)
Parameter 4.75 V to 5.25 V 2.7 V to 3.6 V Unit Description
f
SCLK
2
2 2 MHz max
t
CONVERT
14.5 t
SCLK
14.5 t
SCLK
t
ACQ
1.5 t
SCLK
1.5 t
SCLK
Throughput Time = t
CONVERT
+ t
ACQ
= 16 t
SCLK
t
1
10 10 ns min CS to SCLK Setup Time
t
2
3
30 60 ns max Delay from CS until DOUT 3-State Disabled
t
3
3
75 100 ns max Data Access Time after SCLK Falling Edge
t
4
20 20 ns min Data Setup Time Prior to SCLK Rising Edge
t
5
20 20 ns min Data Valid to SCLK Hold Time
t
6
0.4 t
SCLK
0.4 t
SCLK
ns min SCLK High Pulsewidth
t
7
0.4 t
SCLK
0.4 t
SCLK
ns min SCLK Low Pulsewidth
t
8
4
80 80 ns max CS Rising Edge to DOUT High Impedance
t
9
55µs typ Power-Up Time from Shutdown
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
Mark/Space ratio for the SCLK input is 40/60 to 60/40. See Serial Interface section.
3
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V with V
DD
= 5 V ± 10% and time for an output to
cross 0.4 V or 2.0 V with V
DD
= 3 V ± 10%.
4
t
8
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
8
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
1
(T
A
= T
MIN
to T
MAX
, unless otherwise noted)
1.6V
I
OL
200␮A
200␮A
I
OH
TO
OUTPUT
PIN
C
L
50pF
Figure 1. Load Circuit for Digital Output Timing Specifications
REV. C